How to access individual bits in registers ?
Daku
I have:
parameter DATA_WIDTH = 24;
parameter MAX = 10;
/* Some memory */
reg [0: DATA_WIDTH - 1] dataArray[0 : MAX - 1];
reg [0: DATA_WIDTH - 1] tmp;
Now in a loop, I want to access individual elements of dataArray, and
then manipulate individual bits in each of these.
A statement like :
tmp = dataArray[i];
Generates errors due to register/wire mismatch.
How do I resolve this issue ?
Any hints, suggestions would be greatly appreciated. Thanks in advance
for your help.
gabor
What sort of loop? This statement can't just sit there
by itself. If you have it inside an always block it should
work. Can you post the loop code?
Jason Zheng
Daku <daku...@gmail.com> wrote:
> A statement like :
> tmp = dataArray[i];
> Generates errors due to register/wire mismatch.
Are you sure the error is really referring to this line? tmp was
declared as reg type and this seems alright to me.
~Zheng
pallav
I think it is better to declare registers as reg[DATA_WIDTH-1:0] tmp;
For memories, reg[DATA_WIDTH-1:0] dataArray[0:MAX-1]; Its easier to
think MSB -> LSB in
a register.
As others have stated, seeing the code might help.
Daku
message. I am using Icarus Verilog 0.9.1
module queuetest(clock, rd, wr);
input clock;
input rd;
input wr;
parameter MAX = 10;
parameter DATA_WIDTH = 24;
reg [MAX - 1:0] indexArray;
reg [MAX - 1:0] priorityArray;
reg [DATA_WIDTH - 1:0] dataArray[MAX - 1:0];
reg [DATA_WIDTH - 1:0] tmp;
integer i;
integer j;
integer num;
integer head;
integer tail;
initial
begin
num = 0;
head = 0;
tail = 0;
begin
for(i = 0; i < MAX; i = i + 1)
indexArray[i] = 0;
priorityArray[i] = 0;
tmp = DataArray[i];
end
i = 0;
j = 0;
end
always @ (posedge clock)
begin
if(num < MAX)
begin
if(wr && !rd)
begin
sethead(indexArray);
indexArray[head] = 1;
dataArray[head] = 1;
num <= num + 1;
$display("Data enqueued at %g", head);
end
end
else
$display("queue is full");
end
always @ (negedge clock)
begin
if(num > 0)
begin
if(rd && !wr)
begin
settail(indexArray);
indexArray[tail] = 0;
dataArray[tail] = 0;
num <= num - 1;
$display("Data dequeued from %g", tail);
end
end
else
$display("Queue is empty");
end
task sethead;
input [MAX - 1:0] a;
integer lindex;
begin
for(lindex = 0; lindex < MAX; lindex = lindex +1)
if(a[lindex] == 0) head = lindex; disable sethead;
end
endtask
task settail;
input [MAX - 1:0] a;
integer lindex;
begin
for(lindex = 0; lindex < MAX; lindex = lindex + 1)
if(a[lindex] == 1) tail = lindex; disable settail;
end
endtask
endmodule
The error message is:
/root/verilog/queue.vl:31: error: Unable to bind wire/reg/memory
`DataArray[i]' in `queuetb.qtest'
1 error(s) during elaboration.
My basic problem is how do I access individual bits in a register, or
what is a workaround ?
Thanks in abvance for your help.
glen herrmannsfeldt
> Well, the source code is below, and after that the compile-time error
> message. I am using Icarus Verilog 0.9.1
> module queuetest(clock, rd, wr);
> input clock;
> input rd;
> input wr;
> parameter MAX = 10;
> parameter DATA_WIDTH = 24;
> reg [MAX - 1:0] indexArray;
> reg [MAX - 1:0] priorityArray;
> reg [DATA_WIDTH - 1:0] dataArray[MAX - 1:0];
> reg [DATA_WIDTH - 1:0] tmp;
> The error message is:
> /root/verilog/queue.vl:31: error: Unable to bind wire/reg/memory
> `DataArray[i]' in `queuetb.qtest'
> 1 error(s) during elaboration.
> My basic problem is how do I access individual bits in a register, or
> what is a workaround ?
I am not sure it completely answers your question, but don't
access (set) individual bits. Instead make indexArray and
priorityArray one bit wide memories.
You should read/write whole words of dataArray, which I thought
was what you were doing.
You will find verilog much easier if you think like hardware
instead of like software.
-- glen
sh...@cadence.com
sensitive in Verilog.