Connecting wires together and meaning of assignment

[Mohammed Hamed]

Hi All,

I have two wires that I need to connect together to form a single
net.

eg:
wire n1,n2;

If I use the assignment statement :
assign n1=n2;

I want to make sure that this means just connecting the two wires in
Verilog semantics and that it doesn't involve anything related to
direction. i.e. I want this assignment evaluate to a bidirectional
assignment, so that If n2 will change, n1 will change consequently and
vice versa. Is that possible just using the assign statement ?

Thanks

[tbrkic]

I dont think you can use assign in that way.

But the question is what you want to do. First of all
it is not a good idea to have 2 nets that are connected
to be driving at the same time.

Is n1 or n2 driving something else or are the bidirectional signals?

If they are driving somehthing else and one of them is always
in tristate you can do:

tri n1, n2;
wire n3;

assign n3 = n1;
assign n3 = n2;

If they are bidirectional data you still have to ensure that
one of them is always in tristate and could do like this:

tri n1, n2;
assign n1 = n2;
assign n2 = n1;

Best regards,

Toni

mhel...@yahoo.com (Mohammed Hamed) wrote in message news:<e0d0cbd0.02102...@posting.google.com>...

[Steven Sharp]

mhel...@yahoo.com (Mohammed Hamed) wrote in message news:<e0d0cbd0.02102...@posting.google.com>...

No. That creates a unidirectional connection, with the value of n2
being driven onto n1, but n1 does not affect n2. Your synthesis tool
may decide that they can be a single net, but that is not what will
happen in simulation. The assign acts pretty much like a buffer.

There is a tricky way to get two nets to actually be connected so
that they are the same net. Define an module like the following:

module alias (a, a);
inout a;
endmodule

This module now has two external ports connected to the same
internal net. Then instantiate the module connected to your
two wires:

alias(w1, w2);

The nets are now connected together. There are other variations
of this port-connection approach, but this is the simplest.

You could get a similar effect with a tran primitive, but there
are some small differences, it is less efficient to simulate,
and who knows what your synthesis tool will do with it.

[Mr Nand]

You can do this with a bidirectional pass switch, this is also one way
to model a connector

tran t1 (n1,n2);

If you are trying to model a bidirectional bus, then you just connect
the same wire to both instances and drive the wire accodingly

[David J. Roberts]

mhel...@yahoo.com (Mohammed Hamed) writes:

The verilog HDL "assign" statement is unidirectional. The value of n2
will be driven onto n1 where it will be resolved with any other driver
on n1. Nothing on n1 will make it back to n2. An HDL "assign" is
basically an nmos gate with the gate input tied high.

If you want to short the two wires together use an alias module.

module short(.io1(a),.io2(a));
inout a;
endmodule

--David