Verilog UDP models

[Greg Haynes]

I'm having trouble creating UDP-based models for
sequential cells in an ASIC library. The problem
arises when using the notify signal from a SETUP
timing check to make the output go to X. When
the setup violation occurs (at a clock rising
edge), the notify signal also toggles, and
simultaneous input changes are processed in a
non-specified order in the UDP.

The following example shows how I would like to model
the cell. It is correct except that the output
does NOT go to X when notify toggles due to a setup
violation. I suspect this is because there are two
lines that can apply (if D is 0), lines 2 and 7.
If line 2 is processed last, the output goes to 0
instead of X.

This must be a common problem for anyone using
UDPs as described in the Verilog-XL reference
manual. Does anyone have any suggestions on how
to fix this? (Incidentally, I can make changes
to the table so setup works, but these changes
cause other functional problems.)

primitive dffUDP(qi, CLK, D, notify);
input CLK, D, notify;
output qi;
reg qi;
table
//CLK D notify : Qp : Q ;
f ? ? : 0 : 0 ;
r 0 ? : ? : 0 ;
? 0 ? : 0 : 0 ;
f ? ? : 1 : 1 ;
r 1 ? : ? : 1 ;
? 1 ? : 1 : 1 ;
? ? * : ? : x ;
? * ? : ? : - ;
endtable
endprimitive

Thanks,
-Greg Haynes
UTMC

[Ashutosh Varma]

This problem of event ordering should not normally occur since timing
checks are processed at the last in any time-slot.

So, notify reg toggling should happen at the end of time-step, when all
other signals changes have already been evaluated and scheduled. Because
of intertial scheduling, the notify register schedule should then
over-ride all other previous schedules.

Which simulator are you using?

-Ashutosh

--
Ashutosh Varma Axis Systems
Senior Application Specialist 209 Java Drive
Email: as...@axiscorp.com Sunnyvale, CA 94089
Phone: (408)588-2000 x143 Fax: (408)588-1662

[David A Allen]

You can fix this problem by adding a small delay in the "notify" path
when using the UDP. For example:

module my_flop (Q, D, CLK);

output Q;
input D, CLK;
reg notifier;

dffUDP i0 (QT, D, CLK, timing_err);

buf i1 (Q, QT);

// This buffer helps insure that the UDP outputs an "X" when a
// timing error occurs. Without this buffer, the UDP will have
// multiple inputs changing within a simulation event (the
// signals that generated the timing error, plus the notifier
// signal...)

buf #0.01 tim1 (timing_err, notifier);

specify
// Setup test
specparam Tsu = 1;
specparam Th = 1;
$setuphold(posedge CLK, D, Tsu, Th, notifier);
// Path Delays
specparam Tco = (2,2);
(CLK => Q) = Tco;
endspecify

endmodule

Hope this helps!

Dave Allen
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David A. Allen, Account Manager
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email: dav...@col.hp.com
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