Using arrays of instances
Alfonso Martinez
I've been using the VeriWell simulator from Wellspring (free version)
for a short period of time and I've had problems creating arrays of
instances. One example is shown below (this is taken from the 3rd
Edition of the book by Thomas and Moorby):
module xor8(xout,xin1,xin2);
output [1:8] xout;
input [1:8] xin1,xin2;
xor a[1:8] (xout,xin1,xin2);
endmodule
When I compile, the simulator complains that there is a parse error in
the line that instantiates the vector of XORs, and that it was expecting
a "(".
Could anybody tell me what the cause of this may be? Is this syntax
not supported by the free version of VeriWell? Is it outdated syntax?
If so, how do I instantiate several modules into an array?
Any help on this is appreciated.
Alfonso
Chris Spear
Alfonso Martinez wrote:
> I've been using the VeriWell simulator from Wellspring (free version)
> for a short period of time and I've had problems creating arrays of
> instances. One example is shown below (this is taken from the 3rd
> Edition of the book by Thomas and Moorby):
>
> module xor8(xout,xin1,xin2);
> output [1:8] xout;
> input [1:8] xin1,xin2;
>
> xor a[1:8] (xout,xin1,xin2);
> endmodule
>
> Alfonso
Arrayed instances are not supported by most Verilog simulators, except
for Cadence's Verilog-XL and NC-Verilog.
--------------------------------------------------------------------
Chris Spear Field Applications Engineer
Viewlogic Systems, Inc. Email: sp...@viewlogic.com .. __o
293 Boston Post Road Phone: (508) 303-5252 _`\<,_
Marlboro, MA 01752-4615 Fax: (508) 480-0165 .. (*)/ (*)
--------------------------------------------------------------------
Hans Akerlund
Why not:
assign xor = xin1^xin2;
/Hasse
Hans Akerlund
Why not:
assign xout = xin1^xin2; ???
/Hasse
James Lee
Dave Kelf from Cadence had some additional words on this subject _
though I'd pass along.
>As Chris mentioned, Cadence supports the IEEE 1364 Arrayed Instance feature
>in our Verilog simulators. Here is some info on what they are all about and
>how they
>can be used. Any more questions Alfonso, let us know.
>
>Arrayed Instances
>
>This much requested feature allows a range of instances to be specified in
>a single declaration. For example, the following declaration specifies
>that 8 instances of the module named module1 are connected up to busses b1
>and b2, and a single clock signal.
>
>module1 inst[7:0] (b1[7:0], b2[7:0], clk);
>
>This capability facilitates a number of new operations. Netlists from
>schematic capture systems, which contain iterated instances, may now be
>mapped directly to the Verilog language. A large amount of needless typing
>can be avoided.
>
>Perhaps the most significant benefit is the capability to parameterize
>cells, cutting down on a large number of replication of blocks of logic.
>Combined with the new `Bit Annotation' feature described below, it is now
>possible to specify user-defined models which can be expanded using
>parameters. For example:
>
>module register (in, out, clk);
>
> parameter size = 8; // default block size
>
> input [size:0] in; // variable io widths
> input clk;
> output [size:0] out;
>
> regblock i[size:0] (in,out,clk); // variable instance declaration
>
>endmodule
>
>module regblock (in,out,clk);
>...... // gate representation
>endmodule
>
>The previous module can be applied in the netlist as follows:
>
>wire [9:0] bus1, bus2;
>register #(9) (bus1,bus2);
>
>With the ability to nest arrays to form multi-dimensional structures,
>many block types may be modeled efficiently.
>
>
>========================
>Dave Kelf
>Verilog Product Marketing Manager
>Cadence Design Systems Inc.
>
>Tel: (508) 446 6334
>Email: da...@cadence.com
>========================
-- James
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James M. Lee j...@c118618-a.frmt1.sfba.home.com
Verilog Instructor http://c118618-a.frmt1.sfba.home.com
Author "Verilog Quickstart" ISBN 0-7923-9927-7
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