A couple of questions to all the Verilog experts from a Verilog newbie:
1. What are the implications of coding a flip-flop with both posedge of
clock and negedge of clock in the sensitivity list, ie
always @ (posedge clock or negedge clock or negedge reset)
2. How would the use of the above affect synthesis? Will a design be
synthesizable if it contains RTL with dual edge-triggered clocks?
Thanks very much in advance.
I tried using two flip flops - one driving at posedge, and the other at
negedge of clk.
While you cannot ignore issues resulting from hold times, these are, for the
most part, taken care of by the library vendor and/or the tools used for
synthesis. Most ASIC libraries (and FPGA flip flops) have very small hold
time requirements - some/most are even negative. Furthermore the CLK->Q
propagation time for most flip-flops are usually larger than the hold time
requirements of flip flops. So, assuming you have a "reasonable" clock (one
that doesn't have excessive skew), the CLK->Q time is longer than the worst
case clock skew plus the worst case hold time requirement. In this case, it
is impossible to have a hold time violation. In the cases where this isn't
true, it is still quite rare to have a hold time problem; combinational
logic and even signal routing will all serve to "delay" the change in data
that occurs on the Q of a flip-flop from proagating to the next flip-flop so
that it doesn't violate the hold time requirement.
Finally, synthesis tools understand hold time requirements, and can be asked
to "fix" hold time violations, which they will do by adding delay on paths
from Q->D that would otherwise violate a hold time requirement.
Because of all these reasons, hold time issues can be dealt with without
requiring two different clocks (or any other heroic measures); for your
counter, you should be able to simply code it as
always @(posedge clk)
count <= 0;
if (count == MAX_VAL)
count <= 0;
count <= count + 1'b1;
"Chloe" <chloe_m...@yahoo.co.uk> wrote in message