Multi Dimensional arrays

[Karthikeyan Palinisamy]

I have two multi dimensional arrays in my test environment code
and when I try to assign values of one array to the other I get
this error message

"Error! Illegal reference to memory (a1)
[Verilog-IRETM] "

this is how the part of the code looks like

reg [32:0] a1 [25:0];
reg [32:0] a2 [25:0];

always @(posedge ...)
a1 = a2;

Could any one tell me what I am doing wrong here. Thanks

[Jim Hendry]

Karthikeyan Palinisamy wrote:

I believe you can only assign to particular elements of the memory. ie.
:

while (index >= 0)
a1[index] = s2[index]
index = index + 1
end loop

Hope this helps.

Jim Hendry
Software Engineer
SynaptiCAD, Inc.
http://www.syncad.com

[Mark Curry]

Karthikeyan,

You have discovered one of the gaping holes in verilog.

You can only reference one element of the array
at a time. So, to copy from one
to another, use a for loop.

You also can't declare a 2 dimensional wire,
can't trigger an always block on the whole
element i.e. always @( a1 ), can't have
a multi-dimensional element in a port list,
AND can't reference individual bits from
an array. ( whewww ).

This all stems from the fact ( my guess ), that
when the language was developed, they only
had memories in mind, when using these
contructs.

All this is almost enough for me to grit my
teeth a pick up VHDL full time...

Regards,

Mark Curry

In article <7ikn0m$7kr$1...@simba.ee.pdx.edu>,

Karthikeyan Palinisamy <pali...@ee.pdx.edu> wrote:
>I have two multi dimensional arrays in my test environment code
>and when I try to assign values of one array to the other I get
>this error message
>
>"Error! Illegal reference to memory (a1)
>[Verilog-IRETM] "
>
>this is how the part of the code looks like
>
>reg [32:0] a1 [25:0];
>reg [32:0] a2 [25:0];
>
>always @(posedge ...)
>a1 = a2;
>
>Could any one tell me what I am doing wrong here. Thanks
>

--
Mark Curry
lo...@wolf.pacbell.donkey.net
Remove the animal(s) from the domain name to reply

[Gregor Drodofsky]

Mark Curry wrote:

> Karthikeyan,
>
> You have discovered one of the gaping holes in verilog.
>
> You can only reference one element of the array
> at a time. So, to copy from one
> to another, use a for loop.
>
> You also can't declare a 2 dimensional wire,
> can't trigger an always block on the whole
> element i.e. always @( a1 ), can't have
> a multi-dimensional element in a port list,
> AND can't reference individual bits from
> an array. ( whewww ).
>
> This all stems from the fact ( my guess ), that
> when the language was developed, they only
> had memories in mind, when using these
> contructs.
>
> All this is almost enough for me to grit my
> teeth a pick up VHDL full time...
>
> Regards,
>
> Mark Curry
>

You also can't use 2 dimensional arrays as
an argument of tasks (input, output)
or functions (input). Also 2 dimensional arrays
can't be used as return value of a function.

Regards
Gregor Drodofsky

--
---- Gregor Drodofsky
---- email: peg...@eede.ericsson.se

[Vishal Anand]

There is an article in the latest ISD, "EDA standards for the
millennium" that lists Verilog Multidimensional arrays as one of the
standards pending. Does anybody know where to find the detailed
information regarding this?

Regards,
-Vishal

Mark Curry wrote:

> Karthikeyan,
>
> You have discovered one of the gaping holes in verilog.
>
> You can only reference one element of the array
> at a time. So, to copy from one
> to another, use a for loop.
>
> You also can't declare a 2 dimensional wire,
> can't trigger an always block on the whole
> element i.e. always @( a1 ), can't have
> a multi-dimensional element in a port list,
> AND can't reference individual bits from
> an array. ( whewww ).
>
> This all stems from the fact ( my guess ), that
> when the language was developed, they only
> had memories in mind, when using these
> contructs.
>
> All this is almost enough for me to grit my
> teeth a pick up VHDL full time...
>
> Regards,
>
> Mark Curry
>

[Edward Arthur]

Somewhere off of this link...

http://www.ovi.org/ieee-1364/Welcome.html

[Mark Curry]

Edward,

Thanks for the reference. I did some browsing here, and
it contains some good information.

For those that are interested, the multi-dimensional array
discussions are mostly under the "Minutes June 29, 1998"
heading.

I have some questions regarding the proposal. I'm not
sure where they like feedback, but I do know that
some of the contributers are regulars around here, so
let's hope they're reading...

I refer to section 3.10,
"An element can be assigned a value in a single assignment, but complete or
partial array dimensions cannot. Nor can complete or partial array
dimensions be used to provide a value to an expression. To assign a value
to an element of an array, an index for every dimension shall be specified."

An example is given (which I'll expand upon a little):

reg [7:0] mema[0:255]; // declare a memory mema of 256 eight-bit
// eight-bit registers. The indices
// are 0 to 255

reg arrayb[7:0][0:255]; // declare a two dimentional array of one bit
// registers

mema[ 0 ] = 8'd11; // Legal

arrayb[3][4] = 1'b1; // Legal

mema = 0; // Illegal Syntax - Attempt to write to entire array

arrayb[1] = 0; // Illegal Syntax - Attempt to write to elements
// arrayb[1][0]..[1][255]

arrayb[1][12:31] = 0; // Illegal Syntax - Attempt to write to elements
// [1][12]..[1][31]

I understand that this may be in place to make things more
backward compatible, but is there any other reason? Not
being able to do bit-selects, or in this case, array
selects is painful, and if possible, it'd be better
if it could be avoided. One can't easily swap arrays this
way either, instead having to resort to some awful for
loop. I think all of the above should be legal syntax.

Since the arrays must be fully constrained at compile
time ( no uncontrained arrays like VHDL ), the
compiler should have to trouble indexing into
the correct locations. I think that part
of the proposal should explicitly state
how a multi-dimensional signal gets
mapped down to one dimension - kind of
like how memory is allocated in 'C' for
multi-dimensional arrays. Kind of like a multi-
dimensional array can really be thought of as
a long one-dimensional array with easy indexing.
i.e.

reg arraya [0:255][7:0];
reg [ 7:0 ] first, second;
{ second, first } = arraya; // This will
//assign second = arraya[1][7:0],
// first = arraya[0][7:0]

This way, we wouldn't delve into the VHDL nastiness
of hyper type checking. One has to be
careful in what you're doing, but still
can get the job done!

This leads to another thought, which is not mentioned.
Has any thought be given to sensitivity lists? Currently
one can not have a two dimensional array ( one-dimensional
array of n bit elements ) in a sensitivity list. i.e.

reg [ 7:0 ] y [ 0 : 1023 ];

always @( y ) // Currently illegal syntax.
.. do something with y..

So, now, even with two-dimensional elements, one must
fudge things around quite a bit to use them to
model combinatorial paths. The new proposal explicity
list these multi-dimensional arrays ( which can be regs OR
wires ), as being able to model combinatorial logic.

Your thoughts appreciated - anybody from OVI reading?

In article <3757DACC...@ultranet.com>,

[Michael McNamara]

I have forwarded your comments to the rest of the
1364 standardization group.

It is a bit late at this point to make major changes (we are still
calling it Verilog Standard IEEE 1364-1999, and given how long
standards take, 1999 is just about over for any new work).

I will say we discussed the concept of 'slices' to borrow a term from
perl, as references to objects from an entire array, to some subset
larger than that of on indivdual element of the entire array.

We did not add such a method, for a number of reasons:
1) It is a major change to the language, without a proponent
2) Lack of an implementation to judge feasability
3) Not a synthesisable construct
4) likely other reasons I can't recall ( the meeting was a year ago)

Let me note that having had one of these would have been sufficient
for us to consider the item further; but with none, and with nearly a
thousand other items to consider, we tabled the idea of defining a way
to refer to parts of or to entire arrays for Verilog-1999.

--
/\ Michael McNamara <m...@surefirev.com>
/\// SureFire Verification Inc. 408-374-4100 x 100
/\///\ <http://www.surefirev.com> 408-374-4174 FAX
_\///\/ Formerly Silicon Sorcery
\//\/ Get my verilog emacs mode from
\/ <http://www.surefirev.com/verilog-mode.html>

[Mark Curry]

Michael,

Thanks for passing it on. By the dates on the meetings notes that
I was reading, I'd figured I was too little too late.

Just to kick a dead horse... I can agree with points 1,2, and 4
below. It is a pretty big change. Point 3, however, I believe
is incorrect. I believe that the entire concept is
synthesizable. I think this, because I've done it
by hand - creating long regs's and wires, and indexing
multi-dimensionals into it. Just about every way I could
think of using it, would be synthesizable.

Regards,

Mark

In article <377960C4...@surefirev.com>,

--
Mark Curry
mcu...@ti.com