Master-Slave Register

[Helen]

Hi Here is a simple verilog file I wrote
module reg_msr(ph1, ph2, reset, load, Din,
master,slave);
parameter n = 32; // master slave register
input ph1, ph2, load;
input [n-1:0] Din,reset;
output [n-1:0] master,slave;
reg [n-1:0] master, slave;

always @(posedge ph1 or posedge ph2)
if (reset)
master<=0;
slave<=0;
else
if (ph1)
slave <= master;
else // (at rising edge ph2)
if (load) master <= Din;
endmodule

When I use synplicity for synthesis, it is always
wrong,however, I can use modelsim for simulation with
right answer.
Could you please do me a favor if you know what is
wrong with it.
Thanks alot!

[Mark Curry]

Helen wrote:
>
> Hi Here is a simple verilog file I wrote
> module reg_msr(ph1, ph2, reset, load, Din,
> master,slave);
> parameter n = 32; // master slave register
> input ph1, ph2, load;
> input [n-1:0] Din,reset;
> output [n-1:0] master,slave;
> reg [n-1:0] master, slave;
>
> always @(posedge ph1 or posedge ph2)
> if (reset)
> master<=0;
> slave<=0;
> else
> if (ph1)
> slave <= master;
> else // (at rising edge ph2)
> if (load) master <= Din;
> endmodule
>
> When I use synplicity for synthesis, it is always
> wrong,however, I can use modelsim for simulation with
> right answer.

Helen,

Ok, there's a few things wrong here - I think you
missed a begin end around the reset clause. It's a syntax
error as is - even in modelsim.

But, for simplicity, let's throw out the reset clause for
a moment and focus on the master-slave part.

Since your sensitivity list is calling out "posedge"s,
we can assume you're looking for edge triggered registers,
not level sensitive devices. So, you're code for this
would be:

always @(posedge ph1 or posedge ph2)

if( ph1 )
slave <= master;
else
if( load ) master <= Din;

This part would simulate correctly for you. The problem
is, synthesis tools have "tricks" for recognizing
flip-flops in RTL code. One of the basics for these
tricks, is that for a given procedural block,
you're synthesis tool is going to look for flip-flops
as a function of one clock.

In your master-slave above, the master is a function of ph2,
the slave is a function of ph1. The synthesis tool tries
to map it to one clock, and get's lost.

So, break it out into two blocks. While this may seem
cumbersome, it should make sense if you think about
the hardware you're trying to build. You want one flop
followed by another:

always @(posedge ph2)
if( load )
master <= Din;

always @(posedge ph1)
slave <= master;

Now, this one clock rule per procedural block may seem
bothersome. But the rules for the synthesis tool reconizing
a flop quickly become quite complex once you start adding
more than one clock. One can quicky think up examples
of multi-clock flip-flops that are not really easily realizable
in hardware...

Now, back to the resets. From you're example, it's not clear
what type of reset you're looking for. Is it synchronous or
asynchronous? From the sensitivity list, one thinks
it's synchronous - the procedural block does not "wakeup" on
events from reset. But, in the block, resets take priority
over clocks. So, this is a bit confusing. If you wanted
asynchronous resets, then you need to add the reset
to the sensitivity lists:

always @( posedge ph2 or posedge reset )
if( reset )
master <= 0;
else
if( load )
master <= Din;

always @( posedge ph1 or posedge reset )
if( reset )
slave <= 0;
else
slave <= master;

If you wanted synchronous flops, then just remove
the "or posedge reset" from both sensitivity lists.

Regards,

Mark

[brian]

Hi Helen,

Is This your entire exact code that can be compiled on
simulator?

jun...@yahoo.com (Helen) wrote in message news:<ba3374ff.01081...@posting.google.com>...

> Hi Here is a simple verilog file I wrote
> module reg_msr(ph1, ph2, reset, load, Din,
> master,slave);
> parameter n = 32; // master slave register
> input ph1, ph2, load;

> input [n-1:0] Din,reset;

Really 32bit width 'reset'?

> output [n-1:0] master,slave;
> reg [n-1:0] master, slave;
>
> always @(posedge ph1 or posedge ph2)

> if (reset)
> master<=0;
> slave<=0;

Why don't you blocking these phrase using 'begin-end'?
And Did you adapt synchronous reset with clock ph1 or
ph2 in this flip-flop, did'nt you? Of course this would
not be a problem.

> else
> if (ph1)
> slave <= master;

This condition is Ahhhhh.
Concludly, your code is descripted for one flip-flop using
two clock. But the synthesizer may recognize your code as one
flip-flop has one clock and one reset or set signal. So the
tool may use one of the signals 'ph1, ph2' as flip-flop's
reset/set signal. But even if that case, the phrases that
have ph1 or ph2 condition have lower priority than the phrase
'if (reset)'.
This may give very complicate to synthesizer.

> else // (at rising edge ph2)
> if (load) master <= Din;
> endmodule
>
> When I use synplicity for synthesis, it is always
> wrong,however, I can use modelsim for simulation with
> right answer.
> Could you please do me a favor if you know what is
> wrong with it.
> Thanks alot!

For your reference,

module reg_msr(clock, ph1, ph2, reset, load, Din,

master,slave);
parameter n = 32; // master slave register

input clock, ph1, ph2, load;
input reset;
input [n-1:0] Din;

output [n-1:0] master,slave;
reg [n-1:0] master, slave;

always @(posedge reset or posedge clock)
begin
if(reset)
begin
master <= 'h0;
slave <= 'h0;
end

else
if(ph1)
slave <= master;
else
if(ph2 & load)
master <= Din;
end

Good Luck !!

brian

[Tal]

Try to add begin, end.

always @(posedge ph1 or posedge ph2)
if (reset)

begin
master<=0;
slave<=0;

end

else

"Helen" <jun...@yahoo.com> wrote in message
news:ba3374ff.01081...@posting.google.com...