Variable bit shift

[DW]

I believe that the bit shift operator requires a constant right hand side
operand. Is there a neat and simple way of performing a variable shift - I
can think of some complicated ways of doing it? The shift I need to perform
is a signed shift i.e. <<< or >>>.
DW

[John_H]

I believe I use variable shifts all the time. The variable signed shift
should work just as well. You might, of course, be working with a limited
functionality sim or synth so there isn't an absolute guarantee but you
should be able to get what you need just by coding it.

"DW" <dave_...@hotmail.com> wrote in message
news:cbc8t5$4oa$1$830f...@news.demon.co.uk...

[DW]

"John_H" <johnha...@mail.com> wrote in message
news:sIiCc.16$I25....@news-west.eli.net...

Well, actually, I think Quartus 2 supports it - I think the problem I have
is with Modelsim - can anyone confirm this?
Thanks, DW

[Steven Sharp]

"DW" <dave_...@hotmail.com> wrote in message news:<cbc8t5$4oa$1$830f...@news.demon.co.uk>...

The Verilog language does not require a constant for the shift count. If
your tools aren't allowing it, complain to your vendor or get new tools.
I would expect a reasonable synthesis tool to allow it also, and produce
a barrel shifter (possibly optimized into something simpler depending on
the situation).

Note that calling >>> a "signed shift" is something of a misnomer. It
will perform an arithmetic shift (i.e. extending the sign bit) if the
expression being shifted is signed. It will perform a logical shift
(i.e. shifting in zeroes) if the expression being shifted is unsigned.
In other words, >>> works the way >> works in C.

The older >> always did a logical shift, even for a signed value, and
had to be left that way for backward compatibility. So if you want an
arithmetic shift, use >>>, but also make sure that the value being shifted
is signed.

For a left shift, there is no difference between << and <<<.