syntax error when interface portindentifier is used as specify input

[galen...@gmail.com]

Hi,

I'm running into a syntax error when I try to add timing checks to a SystemVerilog interface. Here's some sample code:

timeunit 1ns;
timeprecision 1ns;

interface PWM_intf ();
logic pulse;
endinterface

module tc_bug (PWM_intf pwm);
specify
$width(posedge pwm.pulse, 10);
endspecify
endmodule


When I try to compile this with the Altera version of Modelsim, I get this error:

# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015
# Start time: 12:41:13 on Mar 10,2016
# vlog -reportprogress 300 -sv vlog_tc_bug.sv
# -- Compiling interface PWM_intf
# -- Compiling module tc_bug
# ** Error: (vlog-13069) vlog_tc_bug.sv(10): near ".": syntax error, unexpected '.', expecting ','.
# End time: 12:41:13 on Mar 10,2016, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# /opt/altera/quartus_lite-15.1/modelsim_ase/linuxaloem/vlog failed.


I also tried it on edaplayground with VCS and Riviera:

Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 12: token is '.'
$width(posedge pwm.pulse, 10);

ERROR VCP7002 "Simple identifier expected for specify terminal: pwm.pulse." "testbench.sv" 12 31
FAILURE "Compile failure 1 Errors 0 Warnings Analysis time: 0[s]."


My reading of the IEEE Std 1800-2012 standard suggests that an interface port identifier should be legal in a timing check.

$width takes a reference_event in the first argument. reference_event is ultimately made up of either a specify_input_terminal_descriptor or a specify_output_terminal_descriptor (page 867). specify_t{in,out}put_terminal_descriptor can be an interface_identifier.port_identifier (page 844).

Why am I getting this error?


thanks,
galen