Accessing DUT internal signals in a SystemVerilog testbench

[okhajut]

VHDL-2008 adds external names to allow hierarchical access to objects that were hidden by scoping rules of previous version of VHDL. This can only be used in testbench code and not synthesis code.

Does SystemVerilog offer a method whereby the user can access signals deep inside the DUT hierarchy to aid in testbench simulation?

[TJ Edmister]

Icarus Verilog allows testbench code to refer to internal variables of a
module, with a syntax like instancename.variablename

...if that's what you mean

[Lyba ashraf]

So this applies only to a specific simulator then?

[Gabor]

No. It's been part of Verilog for a long time. In fact it's one reason
many people have used Verilog as a test bench language even when their
hardware is coded in VHDL.

--
Gabor

[Anssi Saari]

Gabor <nos...@nospam.com> writes:

> No. It's been part of Verilog for a long time. In fact it's one
> reason many people have used Verilog as a test bench language even
> when their hardware is coded in VHDL.

Yes, I remember using hierarchical access back in the 90s in Verilog.

Even with VHDL, it was added in VHDL 2008, 14 years ago. Implementation
in simulators is probably less recent since implementing VHDL 2008 has
been rather slow.