Verilog-XL and $shm_probe() problem

[Jjdur Ukfjg]

After helpful and positive feedback regarding Cadence LDV on Linux,
our company set up an experimental Linux box with Verilog-XL
and NC-Verilog (LDV32 with the latest ISR.)

$shm_probe() works fine with NC-Verilog.

But with Verilog-XL, the resulting wave.trn file only contains
signals (nodes, inputs, outputs) from the very very top level
of the simulation hierarchy.

It's almost as if Verilog-XL *ignores* these commands...
$shm_open...
...
$shm_probe( "<some-hierarchy-level>", "A" );
// I want signals from that hierarchy only, but VerilogXL
// does NOTHING!

If I run the simulation using NC-Verilog, I get the requested
nodes. If I run with Verilog-XL, I get only the top-level
signals...grr...

HOWEVER, using a 'cascade' dump works ok ...

$shm_probe( "<some-hierarchy-level>", "AC" );
// I want signals from that hierarchy and all below!
// VerilogXL dumps the requested nodes!

Does anyone else have this problem? I looked thorugh Cadence's
sourelink database, and found no problem reports of this
nature.

[Utku Ozcan]

> $shm_probe() works fine with NC-Verilog.
>
> But with Verilog-XL, the resulting wave.trn file only contains
> signals (nodes, inputs, outputs) from the very very top level
> of the simulation hierarchy.
>
> It's almost as if Verilog-XL *ignores* these commands...
> $shm_open...
> ...
> $shm_probe( "<some-hierarchy-level>", "A" );
> // I want signals from that hierarchy only, but VerilogXL
> // does NOTHING!
>
> If I run the simulation using NC-Verilog, I get the requested
> nodes. If I run with Verilog-XL, I get only the top-level
> signals...grr...
>
> HOWEVER, using a 'cascade' dump works ok ...

$shm_* implementation of Verilog-XL and NC-Verilog might be
different. And the simulation database filename of yours sounds
like SignalScan output to me, because SignalScan is the only
tool I know so far that generates *.trn files.

> $shm_probe( "<some-hierarchy-level>", "AC" );
> // I want signals from that hierarchy and all below!
> // VerilogXL dumps the requested nodes!

> Does anyone else have this problem? I looked thorugh Cadence's
> sourelink database, and found no problem reports of this
> nature.

Do you have to put double quotes? AFAIK there is no such
requirement for $shm_probe task.

Maybe Cadence do not have development programs on $shm_* commands
any further, therefore they might have put any additional trouble cases.

[Lars Rzymianowicz]

Utku Ozcan wrote:
> $shm_* implementation of Verilog-XL and NC-Verilog might be
> different. And the simulation database filename of yours sounds
> like SignalScan output to me, because SignalScan is the only
> tool I know so far that generates *.trn files.

Utku,
.trn/.dsn is the new db format for SHM, since Sicnalscan was acquired
by Cadence.

> Do you have to put double quotes? AFAIK there is no such
> requirement for $shm_probe task.

At least the manuals do.

Lars
--
Address: University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/

[Srinivasan Venkataramanan]

Hi,
With VERILOG-XL 3.11.s001 under Solaris it works as expected - atleast
produces what I expected. Below is a piece of code (stupid example anyway).
Perhaps a problem with the Linux port? Can you shows us your $shm_probe
call?

"Jjdur Ukfjg" <nn...@htkd.net> wrote in message
news:3B635FA5...@htkd.net...

> It's almost as if Verilog-XL *ignores* these commands...
> $shm_open...
> ...
> $shm_probe( "<some-hierarchy-level>", "A" );
> // I want signals from that hierarchy only, but VerilogXL
> // does NOTHING!
>

I am confused, you said it dumps "from the very very top level" and here
you say NOTHING!

> If I run the simulation using NC-Verilog, I get the requested
> nodes. If I run with Verilog-XL, I get only the top-level
> signals...grr...
>
>
> HOWEVER, using a 'cascade' dump works ok ...
>
> $shm_probe( "<some-hierarchy-level>", "AC" );
> // I want signals from that hierarchy and all below!
> // VerilogXL dumps the requested nodes!

Meaning? Do you get "All signals at <some-hierarchy-level> and the entire
hierarchy beneath"? If yes then I guess the problem is only with "A"
specification and works fine with "AC" ("AS" also?) If so and if your
hierarchy below "<some-hierarchy-level> " is not very deep you can get away
with "AC" (or "AS" slightly better if used with Gate level netlist) - also
try using "is_compression" option with $shm_open.

Regards,
Srini

// My simple example which produced expected results on Solaris..

module test;

reg a,b,c,d;

child u_child (.a(a), .b(b));

initial
begin
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
d <= 1'b0;
#100;

a <= 1'b1;
b <= 1'b0;
c <= 1'b1;
d <= 1'b0;

#100 $stop;

end

initial
begin
$shm_open ("test.trn");
$shm_probe (u_child, "A");
end

endmodule // test

module child (a,b);

input a;
input b;

always @ (a or b)
begin
$display ("A is %b and B is %b \n", a,b);
end

endmodule // child

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India

[Gjsuwk]

> > It's almost as if Verilog-XL *ignores* these commands...
> > $shm_open...
> > ...
> > $shm_probe( "<some-hierarchy-level>", "A" );
> > // I want signals from that hierarchy only, but VerilogXL
> > // does NOTHING!
> >
>
> I am confused, you said it dumps "from the very very top level" and here
> you say NOTHING!

Opps, sorry! I meant that the individual shm_probe command appears
to do nothing. The top-level signals are dumped regardless of what
I do.

> Meaning? Do you get "All signals at <some-hierarchy-level> and the entire
> hierarchy beneath"? If yes then I guess the problem is only with "A"
> specification and works fine with "AC" ("AS" also?) If so and if your
> hierarchy below "<some-hierarchy-level> " is not very deep you can get away
> with "AC" (or "AS" slightly better if used with Gate level netlist) - also
> try using "is_compression" option with $shm_open.

Thanks for the idea...

[James Lee]

I'll bety you have your report backwards.

it worked fine in XL but nothing in NC. If I am correct your problem
is you need to turn on read access. +access+r.

Jjdur Ukfjg <nn...@htkd.net> wrote:

-.-. --.- -.-. --.- -.. . -. .---- -.. -.. -.- -..-. .-- -....
James M. Lee j...@jmlzone.com
Verilog Instructor http://jmlzone.com
Author "Verilog Quickstart" ISBN 0-7923-8515-2
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