Arithmetic Shift operation in verilog
Magnus Karlsson
Jeetendra Kumar wrote:
> How do you the arithmetic shift operation in verilog.
> One way that I have implemented it is by writing
> a small function which does so.
> Can it be done in a smarter way?
>
> jeetend...@analog.com
How about this:
----------------------------------
reg[31:0] x,y;
reg[4:0] n;
always @ (x or n)
y = x>>n | {32{x[31]}}<<(32-n);
----------------------------------
Magnus Karlsson
Apple Computer
Jeetendra Kumar
Hi!
How do you the arithmetic shift operation in verilog.
One way that I have implemented it is by writing
a small function which does so.
Can it be done in a smarter way?
###################################
res = arshft(res+1,1);
// res = (res + 1) >> 1;
-----------------------------
function [31:0] arshft;
input [31:0] x;
input [31:0] y;
reg [31:0] t;
begin
t = x;
repeat(y) begin
t = t >> 1;
t[31] = t[30];
end
arshft = t;
end
endfunction
----------------------------
##################################
please post your replies at:
Bernd Paysan
Jeetendra Kumar wrote:
>
> Hi!
>
> How do you the arithmetic shift operation in verilog.
> One way that I have implemented it is by writing
> a small function which does so.
> Can it be done in a smarter way?
What about
result = x >> y
Works good and generates barrel shifters, if the hardware can implement
them.
--
Bernd Paysan
"Late answers are wrong answers!"
http://www.informatik.tu-muenchen.de/~paysan/
Janick Bergeron
In article <32DFED58...@informatik.tu-muenchen.de>,
Bernd Paysan <pay...@informatik.tu-muenchen.de> wrote:
>Jeetendra Kumar wrote:
>> How do you the arithmetic shift operation in verilog.
>
>
>result = x >> y
>
>Works good and generates barrel shifters, if the hardware can implement
>them.
Ah but this is a *logical* shift, not an arithmeic shift as the sign
(or the polarity of the MSB) is not preserved.
You can't do a generic arithmetic shift right that works on any
width of vectors. The function in the original post was probably
the most generic way of doing it but not very efficient.
If you know the bounds of x and the value of y, the short-hand
notation would be (assuming x[31:0] and y = 5):
x = {{5{x[31]}}, x[31:5]};
--
Janick Bergeron Qualis Design Corporation Ph.: (503) 350-3663
Director of PO Box 4444 Fax: (503) 643-1583
Technology Beaverton, OR, USA, 97075-4444 jan...@qualis.com
VHDL - Verilog - Synthesis - Modelling - Verification - Training
Gerard M Blair
Janick Bergeron wrote:
> If you know the bounds of x and the value of y, the short-hand
> notation would be (assuming x[31:0] and y = 5):
>
> x = {{5{x[31]}}, x[31:5]};
Now, if an RTL module rather than a purely behavioural one
was require, Bergeron's code can be generalized into a
parameterized module thus:
module arithShift(out, in);
parameter size = 32; //default values
parameter shift = 3;
output [size:1] out;
input [size:1] in;
assign out = {{shift{in[size]}}, in[size:shift+1]};
endmodule // arithShift
module testIt;
reg [7:0] in;
wire [7:0] out;
arithShift #(8,3) mod1 (out, in);
initial begin
$monitor("%b -> %b", in, out);
#0 in = 8'b00110011;
#10 in = 8'b11001100;
#20 in = 8'b10000000;
#30 in = 8'b01111111;
#40 $finish;
end // initial begin
endmodule // testIt
--
Gerard M Blair, Senior Lecturer, The Department of Electrical Engineering,
The University of Edinburgh, EH9 3JL, Scotland, UK
Email: ger...@ee.ed.ac.uk - Home page: http://www.ee.ed.ac.uk/~gerard/