Hi,
Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.
I couldn't get NC-verilog to compile the following bit of code.
//4*4 array of byte
wire [7:0] my_array [1:0] [1:0];
So, instead, I used a 'reg', and this compiled OK,
//4*4 array of byte
reg [7:0] my_array [1:0] [1:0];
BUT, when I simulate my design, and open my .trn file in Simvision
(also tried signalscan), I can't seem to see any of my
multi-dimensional signals. I even tried a simple memory like this:
reg [7:0] mem [0:1023].
and even this was not displayed in the "signal/Variables of scope"
window.
Can these tools not display multi-dimensional arrays, or do I have to
set some kind of option somewhere?
p.s I am new to Verilog (ex-VHDL) and the Cadence toolset.
thanks,
Jal.
[snip]
I don't have the experience with simvision, but I had a call in to the
Cadence folks about my 2-D wire troubles.
The array of nets construct
wire [7:0] MyWords [3:0];
is not supported in LDV51 or the current IUS53 release. The IUS54 release
due out sometime in November will provide the full support.
IUS53 - the first release after LDV51 - fixed my problems with conditional
generates and multi-dimensional part select (MyWords[1][1:0]) though bit
select (MyWords[1][2]) reportedly worked in LDV51.
$CDS_INST_DIR/doc/simvision/displaying.html should have the needed
documentaion for it.
Regards,
Ajeetha
http://www.noveldv.com
jalib...@hotmail.com (Jal) wrote in message news:<d8e046e.04100...@posting.google.com>...