Help: How do I change strength procedurally?

Martin Gregory

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Aug 28, 1996, 3:00:00 AM8/28/96

to

Hi,

I want to hard code some test vectors something like this:

initial begin
a = 0 ; io = 0;
# 10
a = 1 ; io = 1;
#10
a = 1 ; io = <weak1>;
#10 // ^^^^^^^^^^^ ????
a = 0 ; io = <weak0>;
// etc ^^^^^^^^^ ????
end

But how can I change the strength of a wire (or anything!) procedurally?

I tried:

assign (weak0, weak1) io = 1;

type of thing, but to no avail - the "(" is a syntax error.

Surely this can be done in Verilog? (It's a piece of cake in VHDL)

Thanks for any advice!

Martin

(email copies of replies most appreciated)

Janick Bergeron

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Aug 29, 1996, 3:00:00 AM8/29/96

to

In article <r8iva29...@asc.sps.mot.com>,

Martin Gregory <mgre...@asc.sps.mot.com> wrote:
>I want to hard code some test vectors something like this:
>
> initial begin
> a = 0 ; io = 0;
> # 10
> a = 1 ; io = 1;
> #10
> a = 1 ; io = <weak1>;
> #10 // ^^^^^^^^^^^ ????
> a = 0 ; io = <weak0>;
> // etc ^^^^^^^^^ ????
> end
>
>But how can I change the strength of a wire (or anything!) procedurally?

>Surely this can be done in Verilog? (It's a piece of cake in VHDL)

It's easy in VHDL because 1164 encodes strength and logic value in
one type/value. Verilog has an orthogonal strength/logic value.

The strength comes from the driver (i.e. the continuous assignment)
and the value come from the driven value (i.e. the reg on the RHS of
the continuous assignment).

You need a more sofisticated vector (vectors! brrrrrr! :-() generator:
Two regs and two continuous assignments, one for the strong values, the
other for the weak values, setting the "strong" reg to 'bz when you want
to drive weak values. Something like:

reg WEAKIO, STRONGIO;
assign (weak1, weak0) io = WEAKIO;
assign io = STRONGIO;

initial
begin
a = 0 ; STRONGIO = 1'b0; WEAKIO = 1'bz;
# 10; // As a matter of style, I prefer to put a semiconlon here
a = 1 ; STRONGIO = 1'b1; WEAKIO = 1'bz;
#10;
a = 1 ; STRONGIO = 1'bz; WEAKIO = 1'b1;
#10;
a = 0 ; STRONGIO = 1'bz; WEAKIO = 1'b0;
// etc
end

Much better coding style (IMHO):

reg WEAKIO, STRONGIO;
assign (weak1, weak0) io = WEAKIO;
assign io = STRONGIO;

task WEAK
input V;
begin
a = V;
STRONGIO = 1'bz;
WEAKIO = V;
#10;
end
endtask

task STRONG
input V;
begin
a = V;
STRONGIO = V;
WEAKIO = 1'bz;
#10;
end
endtask

initial
begin
STRONG(1'b0);
STRONG(1'b1);
WEAK(1'b1);
WEAK(1'b0);
// etc...
end

--
Janick Bergeron Qualis Design Corporation Ph.: (503) 644-9700
Director of PO Box 4444 Fax: (503) 643-1583
Technology Beaverton, OR, USA, 97075-4444 jan...@qualis.com
VHDL - Verilog - Synthesis - Modelling - Verification - Training

Mike McNamara

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Aug 29, 1996, 3:00:00 AM8/29/96

to

In article <r8iva29...@asc.sps.mot.com> Martin Gregory <mgre...@asc.sps.mot.com> writes:

| Hi,

|
| I want to hard code some test vectors something like this:
|
| initial begin
| a = 0 ; io = 0;
| # 10
| a = 1 ; io = 1;
| #10
| a = 1 ; io = <weak1>;
| #10 // ^^^^^^^^^^^ ????
| a = 0 ; io = <weak0>;
| // etc ^^^^^^^^^ ????
| end
|
| But how can I change the strength of a wire (or anything!) procedurally?
|

| Surely this can be done in Verilog? (It's a piece of cake in VHDL)
|

If you want to stick to procedural verilog, use two drivers,
and enable the appropriate strength driver:

module foo;
reg strong_io_driver, weak_io_driver;
wire io;

assign (weak0, weak1) io = weak_io_driver;
assign (strong0, strong1) io = strong_io_driver;

initial begin
weak_io_driver = 1'bz;
strong_io_driver = 1'bz;
#10
strong_io_driver = 1'b0;
a = 1;
#10
strong_io_driver = 1'bz;
weak_io_driver = 1'b1;
a = 0;
#10
...

end
endmodule

You can change the strength of a wire from the pli as well.

-macprocedurally
--
Michael McNamara Silicon Sorcery <http://www.silicon-sorcery.com>
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<http://www.silicon-sorcery.com/verilog-mode.html>