On Monday, October 18, 2021 at 2:09:13 PM UTC-4, tszo...@pacbell.net
> I am working on creating a FPGA implementation of a IBM 7000 series CPU. The bits are numbered with bit 0 as the most significant bit and bit n (n bits per word) as the least significant. Verilog seems to want the opposite order: bit 0 is the least significant bit.
> Does anyone know or has anyone tried numbering bits the other way around in Verilog?
Yes, use VHDL. Bit ordering is user defined in VHDL. The libraries you use are not always general enough to work with reverse bit ordering, but many will work fine.
Can you use the reverse bit ordering for the external interface and use conventional bit ordering for everything internal? I suppose your instruction memory will want to be IBM ordered... which btw, I think you made a typo. It will range [0 to n-1], not [0 to n]. I believe there were some truly deranged companies that used [1 to n] bit ordering.
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