Verilog `include, parameter, function, task accessing
kumar
I need to access functions, tasks, parameters and registers which is
declared in one file and need to access in another file.
For eg.
//file task_funcn.v
//consists of tasks and functions
task one;
....
...
task two;
....
....
parameter to_use = 8;
parameter hex = 3;
....
...
//file name test.v
//file with `include task_funcn.v
`include task_funcn.v
module test;
....
....
always @(x)
one; //task one being called.
two; //task two being called.
endmodule
I need to access the parameters from the file task_funcn.v.
When i compile my design file test.v, i get certain error msg's saying
Undelcared identifiers but actually the parameters are defined in
task_funcn.v file.
`include at the compile time takes the source code of the file being
declared. I do not think in my case it is happening.
Pls help me out in this regards.
Regards
Kumar
Muzaffer Kal
>Hi all,
>I need to access functions, tasks, parameters and registers which is
>declared in one file and need to access in another file.
Parameters are module specific. You can't have a global parameter
which can be seen by all module. For such a purpose, you can use
`define though.
Muzaffer Kal
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
Steven Sharp
> Hi all,
> I need to access functions, tasks, parameters and registers which is
> declared in one file and need to access in another file.
> For eg.
>
> `include task_funcn.v
> module test;
Tasks, functions and parameters must always be declared inside
a module, not outside of them. You should move your `include
inside the module. Then they will be declared in the module
and can be used there, just as if you had typed them in at
that point in the module.