For other reasons, I need the the hierarchical names to be the same
both with and w/o PARAM set which is why I used the label "label" on
both parts of the conditional.
generate if (PARAM=0) begin:label
some_mod mod_inst0 ();
end else begin:label
some_other_mod mod_inst0 ();
> For other reasons, I need the the hierarchical names to be the same
> both with and w/o PARAM set which is why I used the label "label" on
> both parts of the conditional.
Which is why that was explicitly made legal in this situation, where
the two generated scopes are mutually exclusive. This should be fine.
The Verilog-2001 LRM did not specify the creation of a scope for a
conditional generate (though it did specify it for generate for-loops),
and this created a variety of problems. This was fixed for the 2005
LRM, and implementors were advised to follow the 2005 version in their
2001 implementations. The 2005 version allowed leaving off the
explicit label, which still produced a scope but with a
I would guess that some of your tools tried to implement the 2001
specification, but also ignored the named scope that you explicitly
specified, which they should not have done even in the 2001
specification. However, one of the problems with the 2001
specification was that it was unclear about the scoping associated with
generates, so this may be understandable.