Tool to flatten a verilog design.
Varun Jindal
i am looking for a tool, which can flatten my verilog design,
i dont require the various heiarchies in the design and want to
flatten it into single top module design.
is anybody aware of such options in any available tool !?
thanks in advance,
regards
Varun.
Narendran Kumaraguru Nathan
I am really curious to find out why do you want to do such a thing?
The output of DC, after synthesis can be written out in such a form.
Thanks & Regards,
Naren.
varun...@yahoo.com (Varun Jindal) wrote in message news:<a132b4b3.04091...@posting.google.com>...
Petter Gustad
> i am looking for a tool, which can flatten my verilog design,
I wrote such a tool around 1990, it was used to generate netlists for
the Dazix CAD system. Unfortunately, I don't have access the source
anymore. Writing such a program wasn't that difficult. Nowadays it's
probably simpler since you can find parsers available on the net. You
can also run your design through synthesis (works at least in Synopsys
Design Compiler) and flatten the design and write it out to a Verilog
file.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Varun Jindal
be in form of logic gates ... i dont know if it can be done through
the Synopsys Design Compiler.
Say, in my top module i call two modules A and B. Both these modules
contain some information (say) info(A) and info(B).
now, i want the flattened netlist to be in this form
top module .. which contains info(A) and info(B) ... the port list of
top module in both the cases is similar.
i dnt wnat info(A) and info(B) to be decomposed into logic gates.
Regards,
Varun.
Petter Gustad <newsma...@gustad.com> wrote in message news:<87pt4ki...@zener.home.gustad.com>...
Petter Gustad
> Well, if the problem statement requires the flattened netlist NOT to
> be in form of logic gates ... i dont know if it can be done through
> the Synopsys Design Compiler.
You should be able to set the dont_touch attribute on the blocks that
you don't want to be compiled, even though I haven't tried just to
flatten a netlist without doing any compliation in DC myself.
Swapnajit Mittra
> varun...@yahoo.com (Varun Jindal) writes:
>
> > Well, if the problem statement requires the flattened netlist NOT to
> > be in form of logic gates ... i dont know if it can be done through
> > the Synopsys Design Compiler.
>
> You should be able to set the dont_touch attribute on the blocks that
> you don't want to be compiled, even though I haven't tried just to
> flatten a netlist without doing any compliation in DC myself.
>
> Petter
It seems to me that what Varun wants is a flattened *RTL* that
will retain all the RTL constructs (if, always, assign etc.) but
one that will have no hierarchies.
Varun, I can not think of a reason why you would need to do
this, but if this is indeed the case, then:
1. You need to build up the hierarchy tree.
2. Map the local name space within each module to a global
one. An obvious way to do this would be to map a local
variable name to its 'fullpath' (with adequate dose of '\').
I do not know of if such a tool exists, but this looks like an
interesting topic for an MS thesis.
--
SystemVerilog DPI tutorial on Project VeriPage:
http://www.project-veripage.com/dpi_tutorial_1.php
For subscribing to Project VeriPage mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>
Casssod
I have tried doing this in the past, while trying to write a strong
obfuscator for verilog.
I have a project on http://sourceforge.net/projects/hdlobf/ open source.
I plan to add
this in terms of obfuscation but you could probably extract this feature
from the parser.
Regards,
Vispi
"Varun Jindal" <varun...@yahoo.com> wrote in message
news:a132b4b3.04091...@posting.google.com...
Rob Dekker
It's not an easy problem to solve, but it happens in a variety of tools (even though they might not output the 'flattened' form).
One thing to consider is that in order to 'flatten' the Verilog design, you need to unroll generate-loops, and that means that you
need to propagate the values of parameters all the way down from top level to bottom. That also means you need to know the top-level
design, which means that the design must be complete.
Any way, I'm pretty sure that most simulators build a statically elaborated form of the Verilog design, so I would ask VCS and
ModelSim if they can output such a flattened description.
You might be out of luck though, since 'static' elaboration is not the only way (and not an efficient way either) to build a
uniquified model of any HDL design.
Design Compiler does RTL elaboration, which has different objectives, and likely does not build a static model first. But it does
not hurt to ask Synopsys..
Good luck
Rob
"Varun Jindal" <varun...@yahoo.com> wrote in message news:a132b4b3.04091...@posting.google.com...
