How do I control pulse width for frequency divider

[Daku]

Could some Verilog guru please help ? I have a simple divide-by-2
clock divider as:

always @ (posedge clock)
begin
if(divby2count == 2)
begin
divby2count <= 0;
divby2 <= 1;
end
else
begin
divby2count <= divby2count + 1;
divby2 <= 0;
end
end

Is there a simple way to specify and control the pulse width of
divby2, just for the main clock pulse.

Any hints. suggestions would be invaluable. Thanks in advance for your
help.

[gabor]

First of all, the code seems to describe a divide by three counter
since you have states 0, 1, and 2 for divby2count. But as to your
original question, if this is to be synthesized, you can only
set the pulse width to some multiple of the clock period or
possible a half-period if you use both clock edges. For the
case of divide by two, you're stuck with a 50% duty cycle unless
you use both clock edges, in which case you could also get 25%
or 75% assuming a 50% duty cycle clock input.

For simulation, you can make the pulse width anything you
want using delays. Something like:
`timescale 1 ns / 1 ps
always @ (negedge divby2count[0]) begin
divby2 = 1; // immediately set pulse
#10 divby2 = 0; // 10 ns later clear the pulse
end

HTH,
Gabor