Synthesizeable Pulse Generator in Verilog??
Thomas Boehler
has anybody an idea how to describe a synthesizeable pulse generator
in Verilog?
Input Clock with 100MHz, 50% duty cycle
Output pulse with 1ns high periode
Thanks,
Thomas
-- Thomas Boehler Senior Engineer Product Design Infineon Technologies Corp. DRAM Development Alliance (DDA) Tel. (914) 892-9040 Fax (914) 892-9068 emails: thomas....@infineon.com or tboe...@dda.siemens.com
Jonathan Bromley
>
> has anybody an idea how to describe a synthesizeable pulse generator
> in Verilog?
> Input Clock with 100MHz, 50% duty cycle
> Output pulse with 1ns high periode
If you can tell me how to design this in the hardware which
your synthesis tool targets, then I can probably tell you how to
write the design in Verilog. OTOH there is no device I've ever
used with synthesis that is capable of implementing this
reliably (unless, of course, you have a rather fast process
and a 1GHz clock).
Getting a known-width pulse on every edge of a clock requires
you to have carefully controlled delay elements. Gate and
net delays are far too variable (process variations, temperature
and supply dependence) to be satisfactory for this purpose.
Predictable RC delays are not usually part of the macro
library of FPGAs or even most ASIC families :-)
Jonathan Bromley
Hagen Sankowski
try this very dirty code:
// generate async pulse with every posedge
module short_pulses (a, q);
parameter cascading = 3; // means cascading gate delays
// must be a odd number
input a;
// buffer signals
wire [cascading-1:1] inter_buffers;
wire last_buffer;
// 'and' contemporary signal with delayed previous signal
output q;
wire q = a && last_buffer;
// instantiation of buffer gates
not #1
[cascading:1] // generic instantiation
({inter_buffers, last_buffer}, // buffer outputs
{a, inter_buffers}); // buffer inputs
// ATTENTION:
// *GOOD* synthesizer will remove buffers
endmodule
Regards,
hsank.
Hagen Sankowski
sorry, I can't replay a tested solution. My synopsys
isn't still available again; new year, new licence :-(
Be aware that my suggestion is very dirty!
Depends on process, temperature, voltage etc. the pulse length
will be vary up to 100% and more. Nobody knows the variation before.
First Help:
+ check out your synopsys Design Compiler handbook
there is a MIN_DELAY constraint
+ try: MIN_DELAY -from A -to LAST_BUFFER (for path!)
Second Help:
+ check out your synopsys Design Compiler handbook
there is a DONT_TOUCH constraint
+ try: DONT_TOUCH short_pulses (for module!)
Third Help:
+ make a simple module with one NOT gate
+ instantiate that module as buffer at impulse module
+ do your syntheses (don't flatten)
+ as I know, synopsys don't optimizes over module borders
Last Aid:
+ insert the impulse module in the Verilog RTL description
+ do your syntheses (don't flatten) and save Verilog netlist
+ build a Verilog netlist of impulse module by your own
+ replace synthesized module on netlist with your own
+ do your sdf work etc.
I hope this helps.
With greeting from Germany,
hsank.