How to write a barrel shifter in Verilog?

[Davy]

Hi all,

How to write a barrel shifter in Verilog?

Any easy approaches will be appreciated!
Best regards,
Davy

[John_H]

Davy wrote:

See my posting on comp.arch.fpga !

[Neo]

use case statement.

[HDLGuru]

consider the following code:

module arithmatic_shift_right (operand, shiftval, result);
input [31:0] operand;
input [4:0] shiftval;
output [31:0] result;

wire [31:0] im1, im2, im3, im4;

assign im4 = shiftval[4] ? { {16{operand[31]}}, operand[31:16]
} : operand;
assign im3 = shiftval[3] ? { {8{operand[31]}}, im4[31:8] } :
im4;
assign im2 = shiftval[2] ? { {4{operand[31]}}, im3[31:4] } :
im3;
assign im1 = shiftval[1] ? { {2{operand[31]}}, im2[31:2] } :
im2;
assign result = shiftval[0] ? { operand[31], im1[31:1] } : im1;

endmodule

it can be changed
also many synthesis tools can generate barrel shifters when you use
verilog shift operators ( '<<' and '>>' )