SDF Annotation Failures

[David Humphreys]

Hi,

We are using Cadence NC-Sim and always seem to have problems when doing back
annotated VHDL/Verilog simulations with setup/hold checks not being
annotated to our behavioural Verilog
memory models.

For example :-

ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check
(SETUP (negedge A[8]) (COND CS (posedge CL)) (0.54)) of instance
<path removed>.bistDataShell.kesram of module sdm_bd_erco_ram.

The Verilog memory model itself has the following timing definitions for
A[8] :-

$setuphold (posedge CL &&& CS, A[8], tsu_a_cl, th_a_cl, notif_a_adr);

And the SDF file has the following timing definitions for A[8] (I've removed
most of the surrounding
cell definition) :-

(TIMINGCHECK
.
(SETUP (negedge A[8]) (COND CS (posedge CL)) (0.589479:0.589479:0.589485))
(SETUP (posedge A[8]) (COND CS (posedge CL)) (0.607054:0.607123:0.607195))
(HOLD (posedge A[8]) (COND CS (posedge CL)) (0.000000:0.000000:0.000000))
(HOLD (negedge A[8]) (COND CS (posedge CL)) (0.000000:0.000000:0.000000))
.
)

I've been told in the past that this sort of thing is normally caused by
inconsistent Verilog models and
timing files being used when the SDF was generated. Having looked up the
rules as to how the SDF
annotator matches delays in the SDF to those in the code however, I don't
see why it has a problem
annotating these timing checks (apart from the Verilog notifier perhaps).
Other checks on the same cell (e.g. WIDTH, PERIOD) annotate OK so I don't
think it's a problem with the cell instantiation.

Has anybody come across this problem before and solved it ?

Thanks in advance,

Dave Humphreys
Philips PTCL Leuven.

[Martyn Pollard]

"David Humphreys" <david.h...@philips.com> wrote in message
news:3ca46f5e$0$7117$4d4e...@news.be.uu.net...

> Hi,
>
> We are using Cadence NC-Sim and always seem to have problems when doing
back
> annotated VHDL/Verilog simulations with setup/hold checks not being
> annotated to our behavioural Verilog
> memory models.

Hi David, You don't mention which version of NCSim you have or which tool
generated the SDF. I just looked in the database here and there are a few
reported cases of this warning message. The cases I looked at were resolved
to be from syntax errors or other inconsistencies, as you mentioned.

I would suggest calling your local Cadence Hotline so they can spend more
time to help you further.
http://www.cadence.com/support/index.html

Martyn

--
Martyn Pollard

NCSim - High Performance VHDL/Verilog Simulation
NCVHDL, NCVerilog, Verification Cockpit
Cadence Design Systems. http://www.cadence.com/ncsim

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[ehml]

Hi David,

From my past experience, to annotate (negedge A[8]) onto just A[8] is okay in
Verilog, but no-no in VHDL.

I don't know if this is specified in the languages, or just implementation of
tools. May be you want to modify the SDF or RAM model to also match the edge of
A[8].

Regards,
Eng Han