Feb 20, 2022, 4:49:19 PM2/20/22
The SystemVerilog logic type can take one of these possible values per bit: '0', '1', 'X' and 'Z'.
The VHDL std_logic type can take one of these values per bit: '0', '1', 'X', 'Z', along with 'U', 'W', 'L', 'H' and '-'.
I am a user of VHDL and am trying to learn SystemVerilog. I am totally confused that SystemVerilog logic type and the VHDL std_logic types are different in this way. This raises a few questions for me:
1. Why were Verilog and SystemVerilog logic type not made as versatile as VHDL? I am sure this will have some type of drawbacks in certain use cases.
2. In VHDL simulation it is common to have values 'U' and sometimes (only for top level ports) 'L' and 'H'. How are these supposed to be handled in a SystemVerilog design by the simulator?