what is $setup and $hold time?

[Ming-Chung Kao]

Hi, Sir :
When I do pre-layout simulation, the simulator will tell me Timing
violation.
$hold( .....) or $setup(......) . The netlist is synthesized by Design
Compiler.
I don't know what's that and how to overcome it. Where can I find out
the document about those violations.

Thanks for your help.

--
=========================================
NCTU Advance CPU Project Engineer
Ming Chung Kao
TEL : (03) 5712121 - 59253
kao...@act.nctu.edu.tw
=========================================

[raje...@hotmail.com]

Greetings

$setup and $hold are system tasks defined in Verilog LRM.
Here is brief description. Please refer LRM for details.

The $setup Timing Check
The $setup system task has the following format:
$setup( data_event, reference_event, limit, notifier );

$setup arguments
data_event lower bound event
reference_event upper bound event
limit positive constant expression or specparam
notifier register

The $setup timing check reports a timing violation in the following
case:
(time of reference_event)-(time of data_event) < limit
If the reference_event and data_event occur simultaneously,
$setup performs the timing check before it records the new
data_event value, therefore no violation occurs.

The $hold Timing Check
The $hold system task has the following format:
$hold(reference_event,data_event,limit,notifier);

$hold arguments.
reference_event lower bound event
data_event upper bound event
limit positive constant expression or specparam
notifier register

$hold reports a violation in the following case:
(time of data_event) - (time of reference_event) < limit
$hold always records the new reference_event time before it
performs the timing check. Therefore, if simultaneous events occur,
there will be a violation.

You need to check the simulation models for technology library
provided by synthesis vendor. Those will contain setup and hold margin
time numbers.

Hope this helps.
Rajesh Bawankule
(Verilog Center : http://www.angelfire.com/in/rajesh52/verilog.html )

In article <382FC0BA...@act.nctu.edu.tw>,

Sent via Deja.com http://www.deja.com/
Before you buy.

[seenu_...@my-deja.com]

Hi,
If I understand you correctly, you have just synthesised your RTL to
Netlist and are trying to do a post-synthesis, but PRE-LAYOUT
simulation.

Usually at this stage of the design phase, we don't simulate with
exact timing information (as we don't have them yet) and hence these
kind of "timing checks" are meaningless at this stage. Just to
summarise what those two are, they try to check for SETUP and HOLD time
violations for the sequential elements in your design.

How do you "diable" or get rid of these checks ? - well it is tool
dependant, please try an option "+notimingchecks" (which works for
Verilog-XL, if you use NC-Verilog it is during NCELAB, -
NOTIMINGCHECKS). Else please refer to your simulator documentation.

Hope this helps,

Regards,
Seenu-Sridahr