Verilog 2001 File I/O: read large file?

Davy

unread,

Apr 1, 2006, 10:33:49 AM4/1/06

to

Hi all,

I want to read one data @(posedge clock) and compare with my module
output.
The data file may contain one million data and very large.

What's the most efficient way to do it?

My boss told me to use $readmemh, but it seems waste RAM.
Does Verilog 2001 support buffered read like in C? Where can I find the
definition?

BTW, I use Modelsim 6.

Any suggestions will be appreciated!
Best regards,
Davy

Ajeetha

unread,

Apr 1, 2006, 11:22:20 AM4/1/06

to

I would like to understand what kind of design this is to offer
efficient comment/suggestion. On the face of it, the verification
architecture/approach seems to be not well thought out. For e.g. if
this is an image processing system, an offline UNIX diff is a far
better choice.

>> My boss told me to use $readmemh, but it seems waste RAM.

$readmemh can take start and end addr as well. So you could read say
1024 locations at one go, hence using only a 1K memory.

Does that help?

Regards
Ajeetha, CVC
www.noveldv.com

Petter Gustad

unread,

Apr 1, 2006, 5:37:25 PM4/1/06

to

"Davy" <zhus...@gmail.com> writes:

> I want to read one data @(posedge clock) and compare with my module
> output.
> The data file may contain one million data and very large.
>
> What's the most efficient way to do it?

$readmemh might be efficient if you have enough memory. If not, you
might want to do something like:

integer patfile;
event eof;

initial begin
patfile = $fopen("pattern.in", "r");
end

always @(posedge clk) begin
$fscanf(patfile,"%1b%4x",yourbitdata,yoursomeother16data);
if ($feof(patfile)) begin
->eof;
end
end

always @(eof) begin
$fclose(patfile);
end

> Does Verilog 2001 support buffered read like in C? Where can I find the
> definition?

IEEE 1364-2001

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

chr...@gmail.com

unread,

Apr 1, 2006, 4:56:48 PM4/1/06

to

ModelSim is a relatively slow simulator anyway. VCS and NC are faster.
If the design is too much for ModelSim, you might want to consider
those simulators.

sh...@cadence.com

unread,

Apr 1, 2006, 6:30:48 PM4/1/06

to

Verilog-2001 supports $fscanf calls, similar to C fscanf. The degree
to which it is buffered depends on the implementation in the simulator.
The language does not provide for user control of buffering beyond the
$fflush call to flush the buffers. It is likely that the underlying
implementation is using C stdio, and getting the buffering that comes
with that.

Art Stamness

unread,

Apr 1, 2006, 9:18:40 PM4/1/06

to

If the comparison is simple and can be directly mapped bit for bit to a
two dimensional memory, then I would recommend using the $readmem(h/b)
type of comparison. ( and if the memory isn't too big ).

If the simulation needs to be finished exactly when the first
miscompare is detected, because waiting for an offline comparison would
take too much time, then You can follow some of the other suggestions
posted in this thread about $fopen, $fscanf. I find these to be
painfully slow, and not fun to write or debug, but they absolutely can
work.

The simplest answer, if the test isn't really long, and you can afford
to let the test to run to completion before figuring out the correct
answer is to do an offline comparison :

- Write a BFM that will trace the output that you intend to compare to
some file.
- Write a Perl script to do the comparison off-line. (PERL is very
useful for extracting usefull information from large text files,
Verilog is not).

Sometimes the answer to a programming problem in Verilog is to write an
offline checker in perl. Having more tools at your disposal than just
the HDL language itself, will make for faster and more effective
comparison.

And if you are interested in Verilog Verification jobs in the future,
you will find almost all ( that I have ever seen ) , list Verilog and
Perl as the two key tools to doing large scale verification.

-Art

Davy

unread,

Apr 3, 2006, 10:12:39 AM4/3/06

to

Hi,

The problem is the input reference file is too large to load in just
one time.

When I use NC-Verilog and readmemh(), the PC will crash. I think it's
malloc() is not right.

So how to use readmemh() to read file in several parts?

Best regards,
Davy