TMS is not clear as to what data type it is, but I'm pretty sure it's not an array of bits. The code is simply testing it for true or false, not equality to a value.
TMS ? `STATE_1 : `STATE_2
The operator ? checks TMS for "truth"...
> > I don't recall exactly the values of TMS that equate to true and false for TMS, but I expect you get the idea.
> His code just says TMS is an input.
Yeah, Verilog has many, many situations where defaults apply, so TMS is whatever data type is the Verilog default in this case. This is one reason why I don't like Verilog. If you are not intimate with the defaults, you can get some very wrong results.
> > I didn't read the code carefully enough to see the case statement.
> That's exactly what I did and why I had to correct myself. I hate when
> I answer too quickly. Hopefully I didn't do it again.
> > I must be getting old or something.
> I am old.
Getting older is still better than the alternative...
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