Simulation fails with ERROR: [VRFC 10-394] cannot access memory I_In directly

[tpham1...@gmail.com]

Hi All,

I have a VHDL top module that have all ports declared


ENTITY UpConverter IS
PORT (CLK : IN STD_LOGIC;
SYSCLOCK : IN STD_LOGIC; -- 54.
RESET_N : IN STD_LOGIC;
DUC1_shift : IN STD_LOGIC;
DUC2_shift : IN STD_LOGIC;
DUC3_shift : IN STD_LOGIC;
I_In : IN T_Rout_out_Port; -- 16 words of 18 bits, each word is related to a window.
Q_In : IN T_Rout_out_Port; -- 16 words of 18 bits, each word is related to a window.
Pipe_update : IN STD_LOGIC;
Freq_tuning_word : IN STD_LOGIC_VECTOR(22 downto 0) -- SW
);


where T_Rout_out_Port declared in a HDL package file as

type T_Rout_out_Port IS ARRAY (0 to 15) of STD_LOGIC_VECTOR(17 DOWNTO 0);



when I create a verilog testbench to simulate the top. The testbench has contents, for example


initial $readmemb("vectors.dat", I_In);
initial $readmemb("vectors.dat", Q_In);

UpConverter DUC (
.CLK(CLK),
.SYSCLOCK(SYSCLOCK),
.RESET_N(REST_N),
.DUC1_shift(DUC1_shift),
.DUC2_shift(DUC2_shift),
.DUC3_shift(DUC3_shift),
.I_In(I_In_n), // T_Rout_out_Port; -- 16 words of 18 bits, each word is related to a window.
.Q_In(Q_In_n),// : IN T_Rout_out_Port; -- 16 words of 18 bits, each word is related to a window.
.Pipe_update(Pipe_update),
.Freq_tuning_word(Freq_tuning_word)// -- SW Configurable
);


Simulation will fail with errors
ERROR: [VRFC 10-394] cannot access memory I_In directly [UpConverter_tb.v:53]
ERROR: [VRFC 10-394] cannot access memory Q_In directly [/UpConverter_tb.v:54]

Would anyone please help me to resolve the issue.
Many thanks

[GaborSzakacs]

If this is Verilog 2001, and not SystemVerilog, it's not legal to have
an array of vectors as a module port. You might work around this with
an intermediate VHDL wrapper that connects to the DUC with an array,
but then brings each array element to a separate wrapper port to be
accessed by the Verilog test bench.

--
Gabor