ROM initialization?

[John L Redford]

I'd like to set a memory variable to an array of constant values,
i.e. to initialize a variable used as a ROM. That is, I'd like to do
something like:

reg [7:0] rom [3:0] = 1, 2, 5, 9, 23, 56, 2, 5;

I've played with various syntaxes, but can't get it to work. Does
anyone know how to do this? Thanks for any help!

/jlr (John Redford, jredford @ chipwrights.com)

--
/jlr (John Redford, jlr @ world . std . com, http://world.std.com/~jlr)

[Swapnajit Mittra]

In article <FuzDs...@world.std.com>,

Use $readmemb or $readmemh system tasks.
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/

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Before you buy.

[F.Zhu]

WAY 1:
reg [7:0] rom [7:0]; // not [3:0]
initial begin
rom[0] = 1;
rom[1] = 2;
....
rom[7] = 5;
end

WAY 2:
reg [7:0] rom [7:0]; // not [3:0]
initial begin
$readmemh("<filename>", rom); // or use $readmemb
end

WAY 3:
reg [7:0] rom [7:0]; // not [3:0]
initial begin
$sreadmemh(rom, 0, 7, "1 2 5 9 23 56 2 5"); // or use $sreadmemb
end

"John L Redford" <j...@world.std.com> wrote in message
news:FuzDs...@world.std.com...

[F.Zhu]

sorry, way3 should be:

WAY 3:
reg [7:0] rom [7:0]; // not [3:0]
initial begin

$sreadmemh(rom, 0, 7, "1 2 5 9 17 38 2 5"); // or use
$sreadmemb
end

"F.Zhu" <fzh...@hotmail.com> wrote in message
news:8gcovm$au0$1...@info.sta.net.cn...

[Raja Gosula]

I have wondered the same thing for synthesizable code. All solutions
presented in this thread have not addressed those.

The best way a found was to use a function with a case statement inside.

function [7:0] rom
input [3:0] inp
begin
case(inp)
3'b0 : rom = 8'h55
3'b1 : rom = 8'h45
...
endcase
end

[Utku Ozcan]

Raja Gosula wrote:

> I have wondered the same thing for synthesizable code. All solutions
> presented in this thread have not addressed those.
>
> The best way a found was to use a function with a case statement inside.
>

> [code_snipped]

When we talk about synthesizability, I want to give an architecture
specific example.

If your target is a Xilinx FPGA, and if you are using internal RAMs
using design elements in Xilinx Unified Library (a sub-directory in
Xilinx tool installation directory, which includes Verilog files
each of which includes Verilog model of the corresponding design
element), such as RAMB4_x_y (4096 bits of Dual Port RAM, which two
ports can be programmable in any width up to 16), and if you intend
to use these memories as a ROM, then you can mimic a ROM behavior
by setting some initial values used during compilation-time
(this example is for Xilinx Virtex FPGA devices):

INST "chip/decoder/rom_table" INIT_O3=AAAAAAAAAAAAAAAA;

This is a UCF syntax in UCF file (a file that includes constraint
information of the chip, like clock speed, input/output offsets etc).
"chip/decoder/rom_table" is the instantiation name of a RAMB4_x_y
element, which is a RAM in your Verilog code:

RAMB_x_y rom_table (....);

This is architecture-specific, i.e. not portable between the
technologies, but if you stay in the same technology, then
you change initialization values, by just changing the UCF command.
In this way, you don't need to change your Verilog code. This
way you can get rid of compiling your Verilog code and synthesizing
it again. Thus, you can observe the behavior of your chip for
different ROM initial values without having synthesized it.

Utku

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