Verilog 2's Complement Multiplication

[Richard J. Sheldon]

Looking for information and examples on the use of the Verilog language
when modeling a 2's complement multiplier. That is, how do you describe
the multiplication of two 2's complement numbers, resulting in a 2's
complement product, using the Verilog HDL.

Thanks
Richard Sheldon

[Mark Curry]

In article <378A26A3...@lmco.com>,

Here's how I do it - just take care of the sign bit yourself:

function [ product_length - 1 : 0 ] signed_mult;
input [ in_length - 1 : 0 ] a;
input [ in_length - 1 : 0 ] b;

reg [ in_length - 1 : 0 ] positive_a, positive_b;
reg [ product_length - 1 : 0 ] abs_mult;

begin
positive_a = a[ in_length - 1 ] ? -a : a;
positive_b = b[ in_length - 1 ] ? -b : b;
abs_mult = positive_a * positive_b;
signed_mult = ( a ^ b ) ? -abs_mult : abs_mult;
end

endfunction

Didn't actually simulate this - but you get the point. Even
synthesizes too.

Regards,

Mark
mcu...@ti.com

--
Mark Curry
lo...@wolf.pacbell.donkey.net
Remove the animal(s) from the domain name to reply

[Byong-Gon Jeong]

Hi.

In my case.....

module multi (in1,in2,out);
input [4:0] in1,in2;
output [8:0] out; // MSB's of vector in1,in2,out is sign bit

wire [8:0] out;
wire [7:0] mul,cmpmul;
wire [3:0] a,b;
wire sign;

assign a = (in1[4]==0) ? in1[3:0] : ~in1[3:0] + 1'b1;
assign b = (in2[4]==0) ? in2[3:0] : ~in2[3:0] + 1'b1;
assign sign = in1[4] ^ in2[4];

assign mul = a * b;
assign cmpmul = ~mul + 1'b1;
assign out = (sign==0) ? {1'b0,mul} : {1'b1,cmpmul};

endmodule

Above instance, two input values has 5bit width and out has 9bit width.
Input range is -15 ~ +15; output range is -225 ~ +225 .

Regards

Jeong

Richard J. Sheldon 이(가) <378A26A3...@lmco.com> 메시지에서
작성하였습니다...

>Looking for information and examples on the use of the Verilog language
>when modeling a 2's complement multiplier. That is, how do you describe
>the multiplication of two 2's complement numbers, resulting in a 2's
>complement product, using the Verilog HDL.
>

>Thanks
>Richard Sheldon
>