SDF FIle and sdf_annotate
kana...@my-deja.com
I have a problem with sdf back annotation.
I have a gate level netlist and an sdf file(just one!).
In order to back annotate I use sdf_annotate command.
I also have a test case to run with the above.
When I start the simulation(using verilogxl),
the sdf file is back annotated and the sdf.log is
generated. Thereafter the simulation hangs and thus
the testcase is not simulated AT ALL.
This particular testcase ran successfully in rtl
and gate level simulation with no back annotation.
Is there something that I have to specify in my test case,
so that it runs after back annotation?
Anyone knows the reason? I appreciate your
feedback/advice/help/discussion.
Thanx a lot
-regards
kana
(PS: I dont have a config file because I expect the back annotation
to happen with the default values.
Also, in calling the system task-sdf_annotate I just supplied,
the sdf file, the
gate level netlist and the log file as arguments.)
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Ashutosh Varma
with your design.
Debug your design, because of added wire delays in SDF file, some portion of
your design may be malfunctioning.
-Ashutosh
<kana...@my-deja.com> wrote in message news:7l8e8d$o8k$1...@nnrp1.deja.com...
Byong-Gon Jeong
kana...@my-deja.com 이(가) <7l8e8d$o8k$1...@nnrp1.deja.com> 메시지에서
작성하였습니다...
Did you remove Multiple Driven circuit in your design? I suspect this one.
kana...@my-deja.com
> Did you remove Multiple Driven circuit in your design? I suspect this
>one.
Do you mean did I separate multiple clock domains into different
sdf files?
I am not sure what you meant by multiple driven circuits?
Or do you mean 'bus-conflicts'?
please elaborate, because I think you might have a point
here, that will help me,
I appreciate your help
-regards
kana
>In article <Sv%d3.204$zS3....@news.bora.net>,
Byong-Gon Jeong
I'd better explane Multiple Driven Circuit, first.
It can be obtained like following examples....
1+AD4-
reg value+AF8-a+ADs-
......
always +AEA-(eventcondition1) begin
if (???+AD0APQ-1) value+AF8-a +ADwAPQ- value+AF8-b+ADs-
......
end
always +AEA-(eventcondition2) begin
if (???+AD0APQ-1) value+AF8-a +ADwAPQ- value+AF8-c+ADs-
......
end
+AD0APQA+- When value+AF8-a was used in more than two blocks.
2+AD4-
always +AEA-(eventcondition3) begin
......
if (load+AF8-b) value+AF8-a +ADwAPQ- value+AF8-b+ADs-
......
if (load+AF8-c) value+AF8-a +ADwAPQ- value+AF8-c+ADs-
......
end
+AD0APQA+- Although value+AF8-a used in one block, it could be driven several value
at the same time. Above two +ACI-if+ACI- sentences operate individually.
3+AD4-
always +AEA-(eventcondition4) begin
......
if ((load+AF8-b+AD0APQ-1)+AHwAfA-(load+AF8-c+AD0APQ-1)) begin
......
value+AF8-a +ADwAPQ- value+AF8-b+ADs-
value+AF8-a +ADwAPQ- value+AF8-c+ADs-
.......
end
......
end
+AD0APQA+- When value+AF8-a was used twice in one block and in one if condition.
Above examples could be simulated successfully in RTL or Gate level,
according
to each conditions you wrote, but you hard to pass in time driven
simulation.
If the circuit were fabticated, It will occure critical problems. In Power
and Function....
It is hard to explane because of my poor English.....Sorry.
Best regards+ACE-
B.G. Jeong
kanapaali+AEA-my-deja.com +x3Q-(+rAA-) +ADw-7lb1dg+ACQ-ms3+ACQ-1+AEA-nnrp1.deja.com+AD4- +ulTC3MnAxdDBHA-
+x5HBMdVYxgDCtbLIsuQ-...
+AD4-
+AD4APg- Did you remove Multiple Driven circuit in your design? I suspect this
+AD4APg-one.
+AD4-Hello Byong:
+AD4-Do you mean did I separate multiple clock domains into different
+AD4-sdf files?
+AD4-I am not sure what you meant by multiple driven circuits?
+AD4-Or do you mean 'bus-conflicts'?
+AD4-please elaborate, because I think you might have a point
+AD4-here, that will help me,
+AD4-I appreciate your help
+AD4--regards
+AD4-kana
+AD4-
+AD4-
+AD4APg-In article +ADw-Sv+ACU-d3.204+ACQ-zS3.15876+AEA-news.bora.net+AD4-,
+AD4- +ACI-Byong-Gon Jeong+ACI- +ADw-jbg+AEA-asicplaza.co.kr+AD4- wrote:
+AD4APg-
+AD4APg- kanapaali+AEA-my-deja.com +AMAAzA-(+ALAAoQ-) +ADw-7l8e8d+ACQ-o8k+ACQ-1+AEA-nnrp1.deja.com+AD4-
+ALgA3gC9AMMAwQD2AL8AoQC8AK0-
+AD4APg- +AMAA2wC8ALoAxwDPAL8AtAC9AMAAtADPALQA2Q-...
+AD4APg- +AD4-hello Folks:
+AD4APg- +AD4-I have a problem with sdf back annotation.
+AD4APg- +AD4-
+AD4APg- +AD4-I have a gate level netlist and an sdf file(just one+ACE-).
+AD4APg- +AD4-In order to back annotate I use sdf+AF8-annotate command.
+AD4APg- +AD4-I also have a test case to run with the above.
+AD4APg- +AD4-
+AD4APg- +AD4-When I start the simulation(using verilogxl),
+AD4APg- +AD4-the sdf file is back annotated and the sdf.log is
+AD4APg- +AD4-generated. Thereafter the simulation hangs and thus
+AD4APg- +AD4-the testcase is not simulated AT ALL.
+AD4APg- +AD4-This particular testcase ran successfully in rtl
+AD4APg- +AD4-and gate level simulation with no back annotation.
+AD4APg- +AD4-Is there something that I have to specify in my test case,
+AD4APg- +AD4-so that it runs after back annotation?
+AD4APg- +AD4-
+AD4APg- +AD4-Anyone knows the reason? I appreciate your
+AD4APg- +AD4-feedback/advice/help/discussion.
+AD4APg- +AD4-Thanx a lot
+AD4APg- +AD4-
+AD4APg- +AD4--regards
+AD4APg- +AD4-kana
+AD4APg- +AD4-
+AD4APg- +AD4-
+AD4APg- +AD4-(PS: I dont have a config file because I expect the back annotation
+AD4APg- +AD4-to happen with the default values.
+AD4APg- +AD4-Also, in calling the system task-sdf+AF8-annotate I just supplied,
+AD4APg- +AD4-the sdf file, the
+AD4APg- +AD4-gate level netlist and the log file as arguments.)
+AD4APg- +AD4-
+AD4APg- +AD4-
+AD4APg- +AD4-Sent via Deja.com http://www.deja.com/
+AD4APg- +AD4-Share what you know. Learn what you don't.
+AD4APg-
+AD4-
+AD4APg-
+AD4APg-
+AD4-
+AD4-
+AD4-Sent via Deja.com http://www.deja.com/
+AD4-Share what you know. Learn what you don't.
dongsheng zhang
discuss.
By the way, is this sdf file too big so that available memory is 0 byte?
dongsheng
<kana...@my-deja.com> wrote in message news:7l8e8d$o8k$1...@nnrp1.deja.com...
> hello Folks:
> I have a problem with sdf back annotation.
>
> I have a gate level netlist and an sdf file(just one!).
> In order to back annotate I use sdf_annotate command.
> I also have a test case to run with the above.
>
> When I start the simulation(using verilogxl),
> the sdf file is back annotated and the sdf.log is
> generated. Thereafter the simulation hangs and thus
> the testcase is not simulated AT ALL.
> This particular testcase ran successfully in rtl
> and gate level simulation with no back annotation.
> Is there something that I have to specify in my test case,
> so that it runs after back annotation?
>
> Anyone knows the reason? I appreciate your
> feedback/advice/help/discussion.
> Thanx a lot
>
> -regards
> kana
>
>
> (PS: I dont have a config file because I expect the back annotation
> to happen with the default values.
> Also, in calling the system task-sdf_annotate I just supplied,
> the sdf file, the
> gate level netlist and the log file as arguments.)
>
>
> Sent via Deja.com http://www.deja.com/