synthesizable code to Find position of the first occourance
Bhavi Saklecha
of length 24 or more. There are 3 inputs to the block and one output.
inputs
------
start - one clock pulse during which the array is to be scanned for a
set bit.
data - array of 24 bits
clock -
outputs
-------
pointer - pointer to the array
This code is to synthesize in synopsys. The vhdl code works out
to be very simple. But i just cannot do it in verilog without
a brute-force method of doing a case of all combinations !!!
vhdl code without the clock part
--------------------------------
if(start = '1') then
for N in 0 to 24 loop
if(data(N) = '1') then
pointer <= N;
exit;
end if;
end loop;
end if;
verilog that does not synthesize
--------------------------------
if(start = 1) then
for (N=0; N<= 24; N=N+1) begin
if(data(N) = '1') begin
pointer <= N;
N <= 25; //TO exit the loop but doed not synthesize
end;
end;
end;
andi_...@my-deja.com
Approach B simulates faster but some formal verification tools may not
support the "disable" construct.
Approach A:
wire found;
if(start = 1) then
begin
found = 0;
pointer = 0;
for (N=0; N<= 24; N=N+1)
if((data(N) == 1) && !found) begin
pointer = N;
found = 1; //TO exit the loop
end;
end;
Approach B:
if(start = 1) then
begin : THIS_BLOCK
pointer = 0;
for (N=0; N<= 24; N=N+1)
if((data(N) == 1) begin
pointer = N;
disable THIS_BLOCK; //TO exit the loop
end;
end;
Hope it helps,
Andi Carmon
an...@orckit.com
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Share what you know. Learn what you don't.
James E. Stine, Jr.
In terms of actual circutry, you are probably referring to a leading
zero/ones detector. This circuit is used rather extensively in
floating-point addition and subtraction units. You can find an excellent
articles by Professor Oklogdzija available at the following web site about
some novel LZD/LZO detectors at http://www.ece.ucdavis.edu/~vojin/. I hope
that helps
James Stine
jst...@ece.iit.edu
Bhavi Saklecha <bha...@tripath.com> wrote in message
news:378F76B4...@tripath.com...
> N <= 25; file://TO exit the loop but doed not synthesize
> end;
> end;
> end;
>
Dan Hopper
>In article <378F76B4...@tripath.com>,
> bha...@tripath.com wrote:
>> of length 24 or more. There are 3 inputs to the block and one output.
>> This code is to synthesize in synopsys. The vhdl code works out
>> to be very simple. But i just cannot do it in verilog without
>> a brute-force method of doing a case of all combinations !!!
>>
>> vhdl code without the clock part
>> --------------------------------
>>
>> if(start = '1') then
>> for N in 0 to 24 loop
Should really have 0 to 23 or equivalent here.
>> if(data(N) = '1') then
>> pointer <= N;
>> exit;
>> end if;
>> end loop;
>> end if;
>>
>> verilog that does not synthesize
>> --------------------------------
>>
>> if(start = 1) then
>> for (N=0; N<= 24; N=N+1) begin
>> if(data(N) = '1') begin
>> pointer <= N;
>> N <= 25; //TO exit the loop but doed not synthesize
>> end;
>> end;
>> end;
>>
>>
>There are two approaches fully synthesizable and yield the same logic.
>Approach B simulates faster but some formal verification tools may not
>support the "disable" construct.
>
>Approach A:
>
>wire found;
>
>if(start = 1) then
You probably mean equality (==) here and below.
>begin
> found = 0;
> pointer = 0;
> for (N=0; N<= 24; N=N+1)
> if((data(N) == 1) && !found) begin
> pointer = N;
> found = 1; //TO exit the loop
> end;
>end;
>
>
>Approach B:
>if(start = 1) then
>begin : THIS_BLOCK
> pointer = 0;
> for (N=0; N<= 24; N=N+1)
> if((data(N) == 1) begin
> pointer = N;
> disable THIS_BLOCK; //TO exit the loop
> end;
>end;
I'd do it this way. I've taken the liberty of
a) assuming bit 23 is the MSB
b) you're after the location of the first LSB that's set. It was
impossible to tell without the rest of your code what direction
you were going.
c) adding a pointer_valid flag to tell if the output is valid.
Obviously, there are other ways of conveying this information.
d) adding a reset line
module temp (clock, reset_n, start, data, pointer, pointer_valid);
input clock;
input reset_n;
input start;
input [23 : 0] data;
output [4 : 0] pointer;
output pointer_valid;
reg [4 : 0] pointer;
reg pointer_valid;
integer i;
always @(posedge clock)
if (!reset_n)
begin
pointer <= 0;
pointer_valid <= 0;
end
else if (start)
begin
pointer <= 0;
pointer_valid <= 0;
for (i = 23; i >= 0; i = i - 1)
if (data[i] == 1)
begin
pointer <= i;
pointer_valid <= 1;
end
end
else
begin
pointer <= pointer;
pointer_valid <= pointer_valid;
end
endmodule
If you were really after finding the first set MSB, I'd change the
loop to be "for (i = 0; i < 24; i = i + 1)".
Dan