Verilog-XL SDF from command line

[Gordon McGregor]

Hello,
I am experiencing some problems parameterising
a verilog test bench. What I am trying to do
is use a $sdf_annotate compiler directive in
Verilog-XL. I want to be able to pass in the
filename parameter from the command line for the SDF file.

i.e., if I do

`define SDF_FILE "./timing/scan_inserted.sdf"

and then later use

$sdf_annotate('SDF_FILE, other paramters...);

in the testbench source, I have no problems. I would however
like to be able to over-ride the SDF_FILE text macro
from the command line, using the

+define+SDF_FILE=""./timing/some_other.sdf""

syntax. I appear to be having problems due to the use of quotation (")
marks in the above. I would guess I need to have something like

+define+SDF_FILE="\"./timing/some_other.sdf\"" or put quotes around the
$sdf_annotate("'SDF_FILE",...); portion. I have searched the
documentation
for a way to escape quote marks via text macros but cannot find a
reference to
how to achieve this. Can anyone tell me if this is firstly possible,
and if
so how to go about it ? I know I can achieve something similar using
conditional
compilation statements and +defines, but I would prefer an extensable
solution
that doesn't require the testbench to be modified each time a new SDF
file is
required.

i.e.,

`ifdef SDF_1
`define SDF_FILE "./timing/sdf_1.sdf"
`endif
`ifdef SDF_2
`define SDF_FILE "./timing/sdf_2.sdf"
`endif

and so on, and then use an appropriate +define+SDF_# but personally I
find
that rather clumsy and hope there is a better method to achieve what I
want.

thanks,
Gordon
--
Gordon McGregor
Design Engineer
Motorola Programmable Technology Centre
Email: r44...@email.sps.mot.com
Tel: +44 (0)1606 815412

[Gordon McGregor]

I've since solved this problem, using the following:

'+define+SDF_FILE=\"./timing/mR4000_char.sdf\"'

Thanks to those who helped out,

Gordon