parameters in tasks
Joerg Grosse
Is it possible to override a paramater when calling a task?
e.g.
:
:
// here my task
task drive_pin_vector;
parameter BIT_WIDTH = 8;
output[BIT_WIDTH:0] pin_vector;
input[BIT_WIDTH:0] vector_value;
integer i;
begin
for (i=0; i<BIT_WIDTH; i=i+1) begin
drive_pin(pin_vector[i],vector_value[i]);
end
end
endtask
:
:
// here what I thought should work
reg [16:0] my_vector;
:
drive_pin_vector #(16) (my_vector,<new_value>); // does not work
:
Regards,
Joerg
Thomas A. Coonan
drive_pin_vector #(16) (my_vector,<new_value>); // does not work
upcounter #(32) upcountermy (.clk(clk), ..etc..)
I wasn't aware that parameter related to tasks other than that tasks
are assiciates with modules..
Joerg Grosse
>
> i thought parameters were for modules, and that your example:
> drive_pin_vector #(16) (my_vector,<new_value>); // does not work
> is actually more commonly somtheing like:
> upcounter #(32) upcountermy (.clk(clk), ..etc..)
> I wasn't aware that parameter related to tasks other than that tasks
> are assiciates with modules..
Hi Thomas,
I just was wondering - What is the point of having the possibility to define
parameters in tasks when I cannot override them?
Maybe I am missing the point here? :(
Joerg
>
> >Hi,
> >
> >Is it possible to override a paramater when calling a task?
> >
> >e.g.
> > :
> > :
> >// here my task
> > task drive_pin_vector;
> > BIT_WIDTH = 8;
> > output[BIT_WIDTH:0] pin_vector;
> > input[BIT_WIDTH:0] vector_value;
> > integer i;
> > begin
> > for (i=0; i<BIT_WIDTH; i=i+1) begin
> > drive_pin(pin_vector[i],vector_value[i]);
> > end
> > end
> > endtask
> > :
> > :
> >// here what I thought should work
> >reg [16:0] my_vector;
> > :
> >drive_pin_vector #(16) (my_vector,<new_value>); // does not work
> > :
> >
> >Regards,
> >Joerg
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Janick Bergeron
> I just was wondering - What is the point of having the possibility to define
> parameters in tasks when I cannot override them?
It could be overloaded, using a defparam statement (*before* the
simulation is started) as:
defparam ...module_inst_name.drive_pin_vector.BIT_WIDTH = 8;
> > >Is it possible to override a paramater when calling a task?
NO. Because in Verilog, everything is static i.e. the size of
*everything*
is known and cannot be modified once the simulation starts. Resizing
tasks arguments using a parameter would go against that i.e. you'd
need dynamic sizing (i.e. a la unconstrained array in VHDL).
That also why you can't have part selects with expressions
e.g.:
foo = bar[i:j];
The size of the part select cannot be known until simulation time,
which Verilog can't handle.
The solution to your problem is to define your task arguments
as wide as possible, then let Verilog's automatic (and silent)
vector resizing take care of the rest - assuming zero-extensions
and truncation of MSBs will be fine...
BTW, why don't you desribe what you are trying to achieve, not
the mechanism. That way, we could help you find the best way
to do it in Verilog...
interHDL Inc
Joerg Grosse <r44...@email.sps.mot.com> wrote:
>Thomas A. Coonan wrote:
>>
>> i thought parameters were for modules, and that your example:
>> drive_pin_vector #(16) (my_vector,<new_value>); // does not work
>> is actually more commonly somtheing like:
>> upcounter #(32) upcountermy (.clk(clk), ..etc..)
>> I wasn't aware that parameter related to tasks other than that tasks
>> are assiciates with modules..
>
>Hi Thomas,
>
>parameters in tasks when I cannot override them?
>Joerg
>
>
>>
>> >Hi,
>> >
>> >
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email: e...@avanticorp.com
Joerg Grosse
>
> > I just was wondering - What is the point of having the possibility to define
> > parameters in tasks when I cannot override them?
>
> simulation is started) as:
>
> defparam ...module_inst_name.drive_pin_vector.BIT_WIDTH = 8;
>
>
> *everything*
> is known and cannot be modified once the simulation starts. Resizing
> tasks arguments using a parameter would go against that i.e. you'd
> need dynamic sizing (i.e. a la unconstrained array in VHDL).
Janick,
Assuming I could do
drive_pin_vector #(16) ...
drive_pin_vector #(8) ...
I think, the simulator would know before the simulation starts.
Meanwhile, I believe it's the nature of tasks which prevents me to do that (as
already mention by Thomas).
Tasks are not *independent* e.g. they don't maintain the local variables which
makes it impossible to do it (I did not know that before hand).
>
> That also why you can't have part selects with expressions
> e.g.:
>
> foo = bar[i:j];
>
> The size of the part select cannot be known until simulation time,
> which Verilog can't handle.
>
> The solution to your problem is to define your task arguments
> as wide as possible, then let Verilog's automatic (and silent)
> vector resizing take care of the rest - assuming zero-extensions
> and truncation of MSBs will be fine...
Seems to be the only way to make it working for that specific task.
In general, I think the only way to parameterize for reuse is by using modules.
>
> BTW, why don't you desribe what you are trying to achieve, not
> the mechanism. That way, we could help you find the best way
> to do it in Verilog...
because, I would like to understand the mechanism(verilog).
Regards,
Joerg