low power counter design
Jennifer Leng
I want to design a 4-bit counter that has minimum power as possible.
What are the ways to do it?
thanks,
John_H
1) implementing thousands of these counters so every microamp helps,
2) developing an ASIC powered by the light that falls on exposed
silocon,
3) doing a homework problem with a teenie tiny example, or
4) interested in the academics of the transistor level implemention?
So the right people can answer, is your target full custom ASIC?
Standard cell? FPGA? Grapefruit powered CPLD?
Tom Loftus
Some suggestions:
Use a CMOS technology in which static leakage current is low
Use the lowest possible supply voltage
Use the fewest number of transistors (gates)
Use the smallest transistors necessary to drive load at frequency
Switch each bit of the counter at the lowest possible frequency
Minimize the load on the outputs of the counter
Design transistor turn-on/turn-off times during switching to avoid
overlap during which supply rail is essentially shorted
I might have missed something but I think that pretty much covers it.
Tom
Jennifer Leng
interested in architecture change, since I cannot change
process/voltage. And this is for ASIC chip.
It seems gray counter has lower power than binary counter. Is there
other counter that has lower power than gray counter?
thanks,
Mark Schellhorn
comp.lang.verilog and all), and assuming that you have no control over the
physical aspects of the target technology (transistor sizes, operating
voltage, etc.) I'll suggest using a Gray coded counter:
reg [3:0] R_low_power_counter_gray;
always @(posedge clk or negedge resetn) begin
if (!resetn) begin
R_low_power_counter_gray <= 4'd0;
end else begin
case (R_low_power_counter_gray)
4'b0000 : R_low_power_counter_gray <= 4'b0001;
4'b0001 : R_low_power_counter_gray <= 4'b0011;
4'b0011 : R_low_power_counter_gray <= 4'b0010;
4'b0010 : R_low_power_counter_gray <= 4'b0110;
4'b0110 : R_low_power_counter_gray <= 4'b0100;
4'b0110 : R_low_power_counter_gray <= 4'b0101;
4'b0101 : R_low_power_counter_gray <= 4'b0111;
4'b0111 : R_low_power_counter_gray <= 4'b1111;
4'b1111 : R_low_power_counter_gray <= 4'b1101;
4'b1101 : R_low_power_counter_gray <= 4'b1100;
4'b1100 : R_low_power_counter_gray <= 4'b1110;
4'b1110 : R_low_power_counter_gray <= 4'b1010;
4'b1010 : R_low_power_counter_gray <= 4'b1011;
4'b1011 : R_low_power_counter_gray <= 4'b1001;
4'b1001 : R_low_power_counter_gray <= 4'b1000;
4'b1000 : R_low_power_counter_gray <= 4'b0000;
endcase
end
end
It's low power because the minimum number of bits (1) toggle with every
increment. If you need to know the decimal value of the counter at any time
then you can also build a decoder circuit like this, but this will add some
gates to the circuit that toggle and consume power so it's better work
entirely in Gray code if possible.
reg [3:0] low_power_counter_decimal;
always @(R_low_power_counter_gray) begin
case (R_low_power_counter_gray)
4'b0000 : low_power_counter_decimal = 4'b0000;
4'b0001 : low_power_counter_decimal = 4'b0001;
4'b0011 : low_power_counter_decimal = 4'b0010;
4'b0010 : low_power_counter_decimal = 4'b0011;
4'b0110 : low_power_counter_decimal = 4'b0100;
4'b0110 : low_power_counter_decimal = 4'b0101;
4'b0101 : low_power_counter_decimal = 4'b0110;
4'b0111 : low_power_counter_decimal = 4'b0111;
4'b1111 : low_power_counter_decimal = 4'b1000;
4'b1101 : low_power_counter_decimal = 4'b1001;
4'b1100 : low_power_counter_decimal = 4'b1010;
4'b1110 : low_power_counter_decimal = 4'b1011;
4'b1010 : low_power_counter_decimal = 4'b1100;
4'b1011 : low_power_counter_decimal = 4'b1101;
4'b1001 : low_power_counter_decimal = 4'b1110;
4'b1000 : low_power_counter_decimal = 4'b1111;
endcase
end
Mark
"Jennifer Leng" <jl...@california.com> wrote in message
news:79e0c5af.02092...@posting.google.com...
Mark Schellhorn
using latches, an asynchronous circuit, gated clocks, etc. If you're doing a
synchronous ASIC design then a Gray counter with an enable signal or gated
clock is the best I can think of.
"Jennifer Leng" <jl...@california.com> wrote in message
news:79e0c5af.02092...@posting.google.com...
John_H
different. Are there savings in the drive power for more nets?
If the architecture allows, it might be a better power tradeoff to use a
Johnson counter rather than a binary or gray style. This gives one
transition per count like the gray counter does but isn't 4 bits wide.
The decode logic has power issues as well as the larger number of nets
driven by the registers.
You might be able to use a ripple arrangement depending on your timing
needs and control over architecture. If you need a modulo n counter,
there are other techniques that eliminate the need for a terminal count
decode.
There are many approaches to try to reduce system power. Without
knowing the drive requirements of the nets (the fanout is a mystery for
me) or the type of logic driven by those nets or the expense of adding
registers or logic resources to trade off for power, it's an awfully
general question to try to get a specific answer.
The power savings for a 4 bit counter can be no more than 100%. What's
the power value now and what's the target value? As I asked in a
previous post, are you instantiating thousands of these? Are you
running micropower?
Reala
Agree with Tom's suggestion.
From my understand, low power design concern:
1. operation frequency
2. dynamic current (charge and discharge the output cap.)
3. switching current (Direct path from VDD to GND)
4. leakage current
No current = No power
There are many different design.... eg. CMOS, BiCMOS,pass transistor,
Dual-rail domino, Adiabatic.....but I think that we most concern the above 4
factors (factor 3 is very important...it is short circuit)
Reala
"Jennifer Leng" <jl...@california.com> wrote in message
news:79e0c5af.02092...@posting.google.com...
Anthony J Bybell
> It's low power because the minimum number of bits (1) toggle with every
> increment. If you need to know the decimal value of the counter at any time
> then you can also build a decoder circuit like this, but this will add some
> gates to the circuit that toggle and consume power so it's better work
> entirely in Gray code if possible.
Sure the number of final value nets switching is a minimum, but what
about glitch power for intermediate results? For most of the designs
I've seen, latch switching overhead is far greater than for primitive
logic gates. It all depends on the books in your target technology of
course.
Anyway, there is no need for thorough decoding on a gray code ckt as
you can see below:
148:/tmp/q> cat t.v
module top;
reg [0:3] cnt, gray;
integer i;
initial begin
for(i=0;i<16;i=i+1)
begin
cnt = i;
gray = { cnt[0], ^cnt[0:1], ^cnt[1:2], ^cnt[2:3] };
$display("B: %b G: %b", cnt, gray);
end
end
endmodule
149:/tmp/q> verilog t.v | grep 'B:'
B: 0000 G: 0000
B: 0001 G: 0001
B: 0010 G: 0011
B: 0011 G: 0010
B: 0100 G: 0110
B: 0101 G: 0111
B: 0110 G: 0101
B: 0111 G: 0100
B: 1000 G: 1100
B: 1001 G: 1101
B: 1010 G: 1111
B: 1011 G: 1110
B: 1100 G: 1010
B: 1101 G: 1011
B: 1110 G: 1001
B: 1111 G: 1000
Three XOR gates beats a case decoder if you need both sets of values.
=) I leave the inverse (G->B) as an exercise to the reader; the XORs
are on different value bits but is quite similar and goes from
left->right.
regards,
-t
Mark Schellhorn
> about glitch power for intermediate results? For most of the designs
> I've seen, latch switching overhead is far greater than for primitive
> logic gates. It all depends on the books in your target technology of
> course.
Yeah, from what I know it does take more juice to toggle a flop than a gate.
This is why I think that the Gray counter uses minimum power -- only one flop
toggles per increment. Also, because only one input to the gray coding "next
value" logic (my case statement) changes at a time, there should be no
power-sucking intermediate glitches in the ckt. A single input change will
ripple through the gates and any gates that will change value should only do so
once per increment.
For the price of it I'd hope that DC would be able to reduce my case statement
to XOR gates :^), although I wouldn't count on it having seen some bizarre stuff
come out of it in the past.
Jennifer Leng
but more flip-flop. I am not sure which one has less power...Same goes
with one-hot encoding for state machine. Even though no decoding
logic, but has more flip-flop.
Mark Schellhorn <ma...@seawaynetworks.com> wrote in message news:<3D91DAF...@seawaynetworks.com>...
Mark Schellhorn
dissipation of the 4 extra flops is less than the power consumed by the XOR
gates needed for the Gray counter then yes, it would be lower power, at the
expense of 2x the number of flops.
If you need logic to compute the decimal output of the Johnson counter, however,
I think that you would need more decoding gates than you would need if you had
to decode the gray counter value. This would probably negate any tiny power
savings you'd gotten by using Johnson in the first place.
Do you have a power estimation tool and your target library available? Code 'em
up and see which one it thinks is better.
John_H
The logic driven by the Johnson counter probably requires some remapping logic since there are now n/2
bits instead of log2(n), no longer a nice binary-type value.
Your particular application can have a "best" solution, but there is no "best" that covers all
applications. I still personally have trouble fathoming the need for "minimum power" for a single 4 bit
counter. There must be aspects to your situation that aren't communicated to the point that informed
suggestions will provide you with the results you need.