How to model the transmission gate in Verilog without using tran (Behaviour model)

[an...@lsil.com]

Hi !

Can any one help me out in writing a behavioral code for the
transmission gate.

The problem is something like this :


Two INOUT ports are connected by a transmission gate.

--------
--- | | ---
| |------------| |-------------| |
--- | | ---
INOUT1 -------- INOUT2
|
---- ENABLE

TRANSMISSION
Gate

I wanted to model TX gate without using tran.

What I did :
-----------

when Enable is high, I checked for the event on any of the
INOUTS and tried to assign it's value to the other.


CASE 1: if an event occur on INOUT1, and ENABLE is active, I have
assigned it's value to INOUT2. If there is another
event on INOUT1 then conflict is arrising, because
INOUT2 is forcing previous assigned value on INOUT1.


Thanks
Anil

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[Steven Sharp]

You have described a fundamental problem in implementing transmission gates.
A simulator can do this for a tran gate by splitting the connected nets into
separate parts. The tran gate passes through the value of the net before
the contribution from the tran gate. All other readers of the net get the
value of the net after the contribution of the tran gate. You can't do this
yourself, because you have no way to split the net without having to use
two explicit nets. The closest you can get to a behavioral version of

tranif1 (A, B, control);

would be

module my_tran(A_in, A_out, B_in, B_out, control);
input A_in, B_in, control;
output A_out, B_out;

assign A_out = A_in;
assign A_out = control ? B_in : 1'bz;

assign B_out = B_in;
assign B_out = control ? A_in : 1'bz;

endmodule

and connect other outputs on A to A_in and other inputs on A to A_out.
If you have any other inouts on A or B, you need an even more complex
splitting of the nets. You just never realized how much work you were
making the simulator do for you when you used a tran.