How to reference exxternal libraries in Verilog

[Peter Sørensen]

I'm a FPGA-VHDL designer with absolut no knowledge of verilog.
I'm using Mentor FPGA advantage = Renoir+Exemplar+Modelsim.
I need to include a verilog design. This verilog uses/references other
external modules but does not
say which library they are from. I have found out that they are in the
Xilinx primitive library unisim.
To get my mentor tool to handle this properly I need to add the library
name to the module references/instantiations in the
verilog source. How is this done? Can anyone give me an example? I
believe the verilog source is made for synopsys tools
where you just have to read in unisim first. But renoir is able to
handle entities of the same name from multiple libraries and therefore
need a specific lilbrary reference.

Hi
Peter Sørensen

[Stuart Clubb]

Peter,

Renoir handles multiple libraries in VHDL with configurations (in line
or stand-alone). However for Verilog, things are less than useful.
However, as you are just instantiating simulation primitives, you can
do the following:

a) Compile the unisim verilog Library using ModelSim

stick them in a safe place, not in your install tree.
(I do a "vlib unisim_verilog" and compile into "unisim_verilog")

b) Create a standard library mapping in Renoir to provide the pointer
to the unisim_verilog library you just pre-compiled.

This should modify the local modelsim.ini to map the unisim_verilog
for furture reference within ModelSim. Alternatively, you can put
the mapping in your default install modelsim.ini (set it read only
afterwards though)

c) Add a command-line reference for invocation of modelsim to use an
additional search library with the switch:

-L unisim_verilog

Providing that you have have the appropriate dual-language options,
your flow should then be fine.

I type this from memory but I think that's about it.

Cheers
Stuart

For Email remove "NOSPAM" from the address

[Curtis Fischaber]

Hi Peter,

Indeed I think Stuart pretty much hit it on the head.  Xilinx does provide a TCL compile script for you, which I personally find quite handy.  You can find this by doing a search (I used 'compile library') from the Xilinx support site at http://support.xilinx.com.  You will find several solutions - sounds like what you are interested can be found in solution 2561.  I have attached the link for your reference.

If I recall, once this is complete it also does step 'b' - that is - it creates an example modelsim.ini file.  I believe it writes this file into the $modelsim/example directory.

Cheers,
Curtis

[Peter Sørensen]

Thanks for your help. It makes it possible to simulate and synthesise.
as far as I can see, I have been busy doing other things so I haven't
finished this yet!

I also wanted to to import an have the source as graphic if possible.
Here I have learned some thinks. (Nice support from Mentor hotline in UK
also)

First Verilog do not have libraries.
All verilog sources or module interfaces must be loaded into the
simulator/synthesis tool
and then modules are connected by name. So dublicated names of modules
are not allowed in a verilog design.

I have upgraded FPGA advantage to version 4.0 just released, here the
verilog import function has improved greatly.
In version 3.0 the unknown unisim modules where not connected at all. In
4.0 dummy module are created and connected.
Thereby you can have the unisim primitives as synthesis black boxes but
with simulation models, through the rest of the flow.

I pretty sure this is going to work.

Hi Peter