how to find the clk period of a clock

[masoodtahir]

I have an input clock coming into a verilog module. I can find out
from the simulation that it is 300ps (from one rising edge to the
next). My question is, inside the module which has this input clock,
is there a way to capture this clock period into an integer variable?

something like:
always @(posedge clk) time1 = $current_time
always @(negedge clk) time2 = $current_time
always @(posedge clk) clk_period = (time2 - time1)*2;

If there exists a variable something like $current_time, what is the
name of the variable? Or is there some other way that this can be
done? I will appreciate a sample verilog code.

[dbwalk...@gmail.com]

Consider the following...
---------------------

`timescale 1ns/1ns

module measure(
input signal,
output time period
);
time last_time;

always@(posedge signal) begin
period = $time - last_time;
last_time = $time;
end

endmodule

module test;

reg clk;
wire [63:0] per;

measure i_m(clk, per);

always
#50 clk = !clk;

initial begin
$monitor($realtime, per);
clk = 0;
#1000 $finish;
end

endmodule
------------------------------

This will measure the signal to 1ns accuracy. If more accuracy is
desired, then you have to change the first number in the "timescale"
directive to a smaller number (and the second number as well).

David Walker

[Alex]

With your solution:

always @(negedge clk) t_neg = $time;
always @(posedge clk) clk_period = ($time - t_neg)*2;

-Alex

[rabidfruitbat]

Hi,

there have been a few replies to your post but I tought I'd ad my 2c.

On May 24, 8:37 am, masoodtahir <masoodta...@hotmail.com> wrote:
[ snip ]

> My question is, inside the module which has this input clock,
> is there a way to capture this clock period into an integer variable?

integer rising_edge = 0;
integer period = 0;
always @(posedge clk) beginrising_edge = $time;
always @(negedge d_clk) high_period = $time - rising_edge;

integer t;

[rabidfruitbat]

don't you hate it when an emacs keystroke posts something mid edit.