Anyone knows what kind of software we can use to check the RTL code
for synopsys syntax error?
Thanks
Steve
HTH,
Srinivasan
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Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India
http://www.noveldv.com http://www.deeps.org
I don't speak for Intel
"Steve Wang" <sw...@actrans-inc.com> wrote in message
news:2a97b920.03051...@posting.google.com...
Sure, try a synthesis tool such as Design Compiler.
Cheers,
JonB
A tool that I use at work it SpyGlass from Atrenta. We have the VHDL
checker, but it also supports Verilog. It's an extermely powerful linting
tool that basically synthesizes the code to an internal format on which it
then performs every check you can imagine. (RTL code check, combinational
loops, testability issues, ...) There are endless configuration options.
I found it to be very useful once it's configured correctly. It's quite
expensive though.
Tom
"Steve Wang" <sw...@actrans-inc.com> schreef in bericht
news:2a97b920.03051...@posting.google.com...
Thanks for the respond, is there any chaper tools can do this job.
Steve
"Tom Verbeure" <tom_ve...@hot.nospam.mail.com> wrote in message news:<3ed3e60f$0$26696$ba62...@reader1.news.skynet.be>...
http://www.veritools-web.com/undertowsuite.shtml
Also there were quite a few threads on Lint tools in ESNUG, one quick search
yielded http://www.deepchip.com/items/0403-05.html
Visit deepchip.com and do a search for Lint.
HTH,
Srinivasan
"Steve Wang" <sw...@actrans-inc.com> wrote in message
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