$deposit function

[Michael Hitchingham]

I am trying to simulate a verilog testbench that uses a system function,
$deposit, which apparently isn't supported by Model Technologies verilog
simulator. The code comes from a company which uses Synopsys and Cadence (?)
verilog simulators and these programs apparently don't have a problem with
this system function.

Is anyone familiar with the $deposit function or have a PLI representation of
the function?

Thanks,
M.Hitch...

[Swapnajit Mittra]

In article <OLJ4Fp5Y#GA....@rejz.ij.net>, mlh...@ij.net says...

$deposit is a Cadence specific system call and is
not part of IEEE Std. 1364-1995.

It "deposits" a value on a wire - i.e. it
assigns a new value to a wire. But, unlike a 'force'
where the value is retained until a subsequent
'release' is used, or a continuous assignment, where
a value is continuously assigned to a wire, this
assignment is for one-time only. This is equivalent
to a procedural assignment to a register type
variable.

Wires are read-only variables. So, there is no direct
method - using PLI or Verilog - to do this. As a matter
of fact, $deposit is a backdoor method of doing something,
which normal Verilog rules do not permit.

I would suggest that you consider the following
alternatives.

1. Use a control variable in a cont. assignment to
that wire :

assign myWire = (select1) ? deposit_val1 : deposit_val0;

2. Use a combination of procedural and continuous
assignment :

wire [7:0] testWire;
reg [7:0] testReg;

assign testWire = testReg;

initial begin
testReg = 8'b0000_0001;
#100
testReg = 8'b0000_0010;
#100
...
end

Rgds,
- Swapnajit.
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