Parameterizable functions
Subbu Meiyappan
How does one go about writing parameterizable functions in verilog.
Let us say that one needs to write a function whose output width
is variable, and so are the input widths.
Thanks
Subbu Meiyappan
Rick Filipkiewicz
Subbu Meiyappan wrote:
Find a book on Verilog, then look in the table of contents and index for
all things that relate to "parameters".
Abhijit
Well, in Verilog you are allowed to declare parameters within a
function, but there is no way of changing their values.
One roundabout way of doing what you want is to declare the function
in a dummy module and declare the parameters in that module scope. Use
the parameters in the function. Now in the main module (where you want
to use the parameterized function) instantiate the dummy module (one
each for different set of param values) with param override. Use
hierarchical function call to access the function with your desired
value.
I know it is a bad solution, but this seems to be the only way.
--Abhijit
jay mitchell
The general way to go about this is to use the "parameter" function
built into verilog. An example of doing what you'd like could be as
follows:
parameter INPUT_WIDTH = 16;
parameter OUTPUT_WIDTH = 16;
output [OUTPUT_WIDTH - 1:0] sum;
input [INPUT_WIDTH - 1:0] in;
If you're using this for FPGA implementaion you might want to take
advantage of the Library of Parameterizable Modules:
hope this helps,
--jay
Illan
not sure what you mean but "parameterizable function" but assuming
you simple want to change parameters while instantiating that all you
need to do is something llike this :
module test (...
parameter width 10
input [width-1:0] din;
...
endmodule
than when you call the module use somethign like
test #(12) test ( ...
when passing few parameter simple write one after the other with comma
in between.
notice that the order is importent and it is base on the order you
define the parameter in the module.
have a nice day
Illan
subbu_m...@yahoo.com (Subbu Meiyappan) wrote in message news:<dd83a5ad.02011...@posting.google.com>...
Subbu Meiyappan
Maybe I was not clear on my e-mail. I was NOT talking about
parameterizable "module"s. That, as somebody cleverly pointed
out, I could have gotten from books. I was more interested in
the actual "function" s in verilog.
Let us say that I have a module:
module test ();
function [7:0] multXxY;
input [3:0] x,y;
multXxY = x * y;
endfunction
wire [3:0] a;
wire [3:0] b;
wire [7:0] c;
assign c = multXxY(a,b);
endmodule
Now, the problem is that the function is tied to
the multiplication of 4 bit unsigned number to a
4 bit unsigned number. Let us say that I want to
multiply a 6 bit number by 6 bit number in the same
module, then I will have to rewrite the function for
that bit-width. So, my question is, is there a way
in Verilog to write a function whereby the function
derives the necesary widths by the way of calling.
In other words, if I write the function as shown below:
function [out_width-1:0] multXxY;
input [x_wdith-1:0] x;
input [y_width-1:0] y;
reg [x_width+y_width-1:0] result; // same as out width
result = x * y;
multXxY = result;
endfunction
can it derive the widths by the width of the
calling assignment's arguments?
Subbu
Parvathy Uma
The long answer is that a verilog function is not like a C function. It is statically elaborated in a simulator. In
other words the memory for a function's return value
and all its input values is allocated only once. So, if you have only one instantiation of the function , then you get
only one return width and only one input width, which depending on the simulator may be the first or the last call to
the function(or something else too)
The same is true for verilog tasks, which is why you have to be real careful about not calling a task before it returns,
or else input and output values can get overwritten.
Hope this helps.
-Uma
Subbu Meiyappan
when I call a function from within my RTL with variable width
values, the compiler (and/or the simulator) has all the information
it needs about the width of the arguments and what not to
correctly elabortate and even place the function inline if
necessary. Don't see why it cannot work.
Thanks anyways,
Subbu
Parvathy Uma <parvat...@verizon.net> wrote in message news:<3C4A2132...@verizon.net>...
jay mitchell
the widths at compile time with the same define syntax we posted
earlier. If you are trying to say that you have a function that has
the ability to dynamically allocate bus widths at run-time, then you
have a different problem. Since verilog is designed to ultimately
produce synthesized hardware, there's no real way to have dynamic
buswidths.
If you'd like to use this function several times with different widths
for each use, why not just create your function as a parameterizable
module instead?
--jay
Parvathy Uma
later. And all of verilog is very much oriented towards hardware.
Well, my theory (it is a theory, I don't know for sure) is that since functions
have a hardware implementation, the way it is implemented in verilog makes
sense. If you want more of the blocks that implement the functions, or if you
want different parameter widths, you encapsulate them in a module and instantiate them multiple times.
-Uma
VhdlCohen
>for each use, why not just create your function as a parameterizable
>module instead?
attributes (e.g.' 'length, 'range, 'high, 'low, ...)
example (VHDL)
function Mult( A : Std_logic_Vector, -- unconstrained array
B : Std_Logic_Vector) return Std_Logic_Vector is
variable Av : Std_logic_Vector(A'length -1 downto 0);
variable Bv : Std_logic_Vector(B'length -1 downto 0);
variable Rv : Std_logic_Vector(A'length + B'length -1 downto 0);
begin
Rv := A * B;
return Rv;
end function Mult;
Length of vector is now depends on the lenght of the actual parameter.
Perhaps next version of Verilog may add such a feature.
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* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
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* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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