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Random numbers with Verilog

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Jim

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Apr 19, 1996, 3:00:00 AM4/19/96
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I've written a test bench that generates pseudo-random stimuli. It has
been difficult to determine just how to generate pseudo-random numbers in
Verilog (specifically, with the VCS simulator). The OVI Verilog LRM 2.0
mentions that there is a system task called $random, but has no further
documentation on its usage. The Chronologic documentation also does not
describe random number generation. The tech. support person I spoke to
there didn't know anything about it either.

So, for doing random tests, what's a good way to generate random numbers
in Verilog? (Besides simulating an LFSR.)

Thanks,
Jim O'Sullivan

Jeff Wilcox

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Apr 22, 1996, 3:00:00 AM4/22/96
to
In article <josullivD...@netcom.com>, josu...@netcom.com (Jim) writes:
[snip]

|> So, for doing random tests, what's a good way to generate random numbers
|> in Verilog? (Besides simulating an LFSR.)
|>

The $random function works nicely as a pseudo-random generator. It will
generate a 32-bit value. It can be initialized via a previously set reg,
integer, or time variable. Thus, there are two ways to call it:
// 1)
$random; // no seed
// 2)
reg seed;
seed = 32'h0;
$random(seed); // seeded call.

|> Thanks,
|> Jim O'Sullivan
|>
|>
Hope it helps,
Jeff Wilcox

Michael McNamara

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Apr 22, 1996, 3:00:00 AM4/22/96
to

In article <josullivD...@netcom.com> posted on Fri, 19 Apr 1996
josu...@netcom.com (Jim) writes:
> From: josu...@netcom.com (Jim)
> Date: Fri, 19 Apr 1996 19:16:11 GMT

>
> I've written a test bench that generates pseudo-random stimuli. It has
> been difficult to determine just how to generate pseudo-random numbers in
> Verilog (specifically, with the VCS simulator). The OVI Verilog LRM 2.0
> mentions that there is a system task called $random, but has no further
> documentation on its usage. The Chronologic documentation also does not
> describe random number generation. The tech. support person I spoke to
> there didn't know anything about it either.

A sad state of affairs, that.


>
> So, for doing random tests, what's a good way to generate random numbers
> in Verilog? (Besides simulating an LFSR.)
>

The IEEE 1364 specification is pretty good here:
[[

14.10.1 $random function

Syntax:
$random[(seed)];

The system function $random provides a mechanisim for generating
random numbers. The function returns a new 32 bit random number each
time it is called. The random number is a signed integer; it can be
positive or negative. For further information on probabalisitc random
numbers, see section 14.10.2.

The seed parameter controls the numbers that $random returns. The
seed parameter must be either a register an integer or a time
variable. The seed should be assigned to this variable prior to
calling $random.

]]

[Here I would add: "One can use a set of seed variables to obtain a
set of distinct independent random number generators. Each time
$random is called with a particular seed variable, it returns the next
random number from that sequence. The random number generator is
psuedo random, as it will return the same sequence of random numbers
if initialized to the same seed value. $random alters the value of
the seed variable passed to it."]


Examples are then given, showing that rand = $random % 60; returns
numbers between -59 and 59, and that rand = {$random} % 60; returns
numbers from 0 to 59. (the {} interpretes the value of $random as a
unsigned value)

Section 14.10.2 discusses the probabalistic random number functions:
$dist_uniform, $dist_normal, $dist_exponential, $dist_poisson,
$dist_chi_square, $dist_t and $dist_errlang. If you are interested in
these more refined random number generators, consult the manual, as
well as a probability textbook.

> Thanks,
> Jim O'Sullivan

As I've posted before, you really should pick up a copy of the
IEEE-1364 specification; check out <http://www.ieee.org>.

In particular, you want DS5408, which costs $65 to IEEE members, $81
to non IEEE members, and is the DRAFT IEEE 1364 specification. It is
an approved draft, and is undergoing final IEEE editing and
typesetting.

More information on how to order is available at:
<http://stdsbbs.ieee.org/faqs/order.html>

-mac
--
Michael McNamara
Silicon Sorcery
m...@mti.sgi.com

Gerard M Blair

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Apr 23, 1996, 3:00:00 AM4/23/96
to

The P1364 **DRAFT** standard (Oct 1995) specifies:

$random[(seed)]

The system function $random ... returns a new 32-bit random number
each time it is called ... a signed integer, it can be positive or
negative.

The seed parameter controls the numbers that $random returns .. [and] must
be either a ragister, an integer or a time variable.

To gain a number in the range [(-b + 1) : (b - 1)] (let us say b = 60):

reg [23:0] rand;


rand = $random % 60;

To get a positive value [0: (b-1)] (let us say b = 60):

reg [23:0] rand;


rand = {$random} % 60;


There are then defined functions in the form of
$dist_XXXX

where XXX may be uniform, nornal, exponetial, poisson, chi_square, t, erlang
providing functions for random numbers with different distributions.

Note two things:

1) there is no stipulation as to the algorithm used to produce these
therefore there is no guarantee that the same sequence will be generated
on different simulaters (or even different versions of the same simulater)

2) these are in a draft standard - the secification in any current simulater
may differ


--
Gerard M Blair, Senior Lecturer, The Department of Electrical Engineering,
The University of Edinburgh, Scotland, UK
Email: ger...@ee.ed.ac.uk - Home page: http://www.ee.ed.ac.uk/~gerard/


Chong Guan Tan

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Apr 30, 1996, 3:00:00 AM4/30/96
to


The purpose of a random number generator is to generate "random number",
preferably in an unpredictable way. Assuming a sepcific sequence to
be generated from a random number generator makes it "not so random",
and is likely to run into problem when the environment is changed.

The algorithm used in Verilog-XL is a trade secret of Cadence design
system, and was not available when the the 1346 folks drafted the
standard. Anyway, even with the same algorithm, two simulators may
still creates differences in simulation by providing differrent
"visible sequence". This is mainly caused by different event
scheduling and optimization strategy applied in the simulators.

A solution to the problem is to not tackle the random number generator,
but to attack the design by making it random number neutral, by various
means.

tan
consultant
Silicon Sorcery
t...@webnexus.com

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