Mixing these assignments in Verilog is often a good idea, despite what people say, because it keeps the relevant code in a single process and makes it easier to follow. Observe these rules:
1. Declare the combinational variable inside the process so it can't be used outside the process.
2. Ensure that it always gets assigned so that latches aren't inferred.
3. Name it with a suffix like "_var".
4. Use blocking assignments for it.
always@(posedge clk) begin
int sum_var; // declare inside
sum_var = 0; // give it a default
for (int kk=0; kk<8; kk++)
sum_var += input_bus[kk]; // blocking assignment
out_reg <= sum_var; // transfer to clocked reg using nonblocking