Problem using genvar for 2 different FOR loop

[sar...@gmail.com]

Hi all,

I am trying to write a code where parameter 'approx' can be changed from outside of the module RCA1.
Default value of approx is zero. If it is greater than zero then RCA1 module will go through 2 different types of for loops and create module instance name accordingly.

If I run this code It says rr block name is already defined. If I change the block name for 2 different for loop then no syntax error generates but if I try to see the schematic view then nothing appears.


Please help me with this situation.
Thanks

...........................

module tb1;

parameter n=3;
reg [n:0] a,b;
reg c,approx;
wire [n+1:0] s;



RCA1 #(.approx(1)) rca1(a,b,c,s);

endmodule
................................................

module FA(a,b,cin,s,cout);
input a,b,cin;
output s,cout;

assign s=a^b^cin;
assign cout=(a&b)|(b&cin) | (a&cin);

endmodule

module RCA1(p,q,ci,r);

input [3:0] p,q;
input ci;
output [4:0] r;

parameter approx=0;

wire [4:0] carry;

assign carry[0]=ci;

genvar i;
genvar j;
generate
for (i=0;i<approx;i=i+1) begin: rr
FA fa(p[i],q[i],carry[i],r[i],carry[i+1]);
end

for (j=approx;j<4;j=j+1) begin: rr
FA fa(p[j],q[j],carry[j],r[j],carry[j+1]);
end
endgenerate



assign r[4]=carry[5];

endmodule

[GaborSzakacs]

sar...@gmail.com wrote:
> Hi all,
>
> I am trying to write a code where parameter 'approx' can be changed from outside of the module RCA1.
> Default value of approx is zero. If it is greater than zero then RCA1 module will go through 2 different types of for loops and create module instance name accordingly.
>
> If I run this code It says rr block name is already defined. If I change the block name for 2 different for loop then no syntax error generates but if I try to see the schematic view then nothing appears.
>
>
> Please help me with this situation.
> Thanks
>

> ............................

>
> module tb1;
>
> parameter n=3;
> reg [n:0] a,b;
> reg c,approx;
> wire [n+1:0] s;
>
>
>
> RCA1 #(.approx(1)) rca1(a,b,c,s);
>
> endmodule

> .................................................

You can't reuse a block name in the same context. So if you
don't want this to be a single loop, you need to use a different
name for the second one.

As for why you don't see anything when you try to see the
schematic view, I have no idea, especially since you didn't
even say what tools you're using.

On the other hand, as written there is no difference between the
two generate loops other than the genvar used. So in effect you
have the equivalent of (assuming 0 <= approx < 4):

for (i=0;i<4;i=i+1) begin: rr
. . .

--
Gabor

[Farhana Sharmin Snigdha]

Thanks a lot for your reply.

Actually there will be 2 different sets of equation for 2 different FOR loop. I was just trying to run this one first to know whether this script simulates or not.

I am using 2 different block names now and it operates perfectly with default value of parameter "approx=0'.
But when I try to pass different value it does not work.
RCA1 #(.approx(1)) rca1(a,b,c,s);

Is this proper a way to pass value of the parameter. I need to pass this 'approx' value from 'tb1.v' module. Is there any other way to do this?

Thanks

[GaborSzakacs]

You seem to be mixing Verilog 95 and Verilog 2001 port syntaxes here.
Assuming you want to stick with the old Verilog 95 syntax, you should
write:

RCA1 rca1 (a,b,c,s);
defparam rca1.approx = 1;

For Verilog 2001, it's best to stick with named port associations,
so if you have the module declaration:

module RCA1(p,q,ci,r);

Then you'd write:

RCA1 #(.approx(1)) rca1 (.p (a),.q (b),.c (c),.s (s));

As originally written I think some compilers would take issue
with the mix of named association for the parameter "ports" and
positional association for the module ports.

Still you didn't say how "it didn't work." Did you get an error?
What tools are you running?

--
Gabor