Multiple assignment statements

[Shaun Jackman]

Is it legal to have multiple assignment statements for the same wire? For example, what's the effect of the following snippet?

module foo(input zero, one, output x);
assign x = zero ? 1'b0 : 1'bZ;
assign x = one ? 1'b1 : 1'bZ;

Cheers,
Shaun

[Cary R.]

I'm always baffled by these type of questions. Did you try this on your
simulator? Did it complain about these statements? Did it produce a
result different than you expected?

FYI the answer is yes this is perfectly acceptable and works as one
would expect. One point to remember is that the assign may be executed
in a different delta cycle then a change to the one/zero variables so
you need to add some delay after changing the inputs and when you look
at/verify the output. This is normal behavior for a continuous
assignment and something that people often make mistakes on. Here's your
basic code with tests for many of the common cases. Writing code like
this is important when you are trying to understand how things work. For
example remove the delays and things don't work as expected.

Cary

module top;
wire res;
reg zero, one, pass;

assign res = zero ? 1'b0 : 1'bz;
assign res = one ? 1'b1 : 1'bz;

initial begin
pass = 1'b1;

// An undefined control bit mixes the true and false clause giving
// 1'b0 for the first assign and 1'b1 for the second assign. These
// then resolves to 1'bx.
// Always add a delay to allow the CA to propagate.
#1;
if (res !== 1'bx) begin
$display("Failed X (T0) test, got %b", res);
pass = 1'b0;
end

zero = 1'b0;
one = 1'b0;
#1;
if (res !== 1'bz) begin
$display("Failed Z test, got %b", res);
pass = 1'b0;
end

zero = 1'b1;
one = 1'b0;
#1;
if (res !== 1'b0) begin
$display("Failed 0 test, got %b", res);
pass = 1'b0;
end

zero = 1'b0;
one = 1'b1;
#1;
if (res !== 1'b1) begin
$display("Failed 1 test, got %b", res);
pass = 1'b0;
end

zero = 1'b1;
one = 1'b1;
#1;
if (res !== 1'bx) begin
$display("Failed X test, got %b", res);
pass = 1'b0;
end

if (pass) $display("PASSED");
end
endmodule

[Shaun Jackman]

On Thursday, July 21, 2011 10:02:33 AM UTC-7, Cary R. wrote:
> On 7/20/2011 10:20 PM, Shaun Jackman wrote:
> > Is it legal to have multiple assignment statements for the same wire?
> > For example, what's the effect of the following snippet?
> >
> > module foo(input zero, one, output x);
> > assign x = zero ? 1'b0 : 1'bZ;
> > assign x = one ? 1'b1 : 1'bZ;
>
> I'm always baffled by these type of questions. Did you try this on your
> simulator? Did it complain about these statements? Did it produce a
> result different than you expected?
>
> FYI the answer is yes this is perfectly acceptable and works as one
> would expect. One point to remember is that the assign may be executed
> in a different delta cycle then a change to the one/zero variables so
> you need to add some delay after changing the inputs and when you look
> at/verify the output. This is normal behavior for a continuous
> assignment and something that people often make mistakes on. Here's your
> basic code with tests for many of the common cases. Writing code like
> this is important when you are trying to understand how things work. For
> example remove the delays and things don't work as expected.
>
> Cary

...

Hi Cary,

I found this case in some production code that I had to open up five years down the road. It behaves as expected on real hardware, but I wasn't convinced that it was in fact legal code, and had difficulty answering this question using Google. My compiler accepted it, but I've found that `My compiler accepted it' is not a good proxy for `This is legal code'. From your truth table, it does behave as I expected.

Thanks for the clarification,
Shaun