How to autoamatically generate "input/output" statements from verilog statement.
Srinivas Lingam - DPG/FDC
Hi,
If i have a verilog statement
assign A = B + C | D;
Can i some how automatically generate:
-------
input B;
input C;
input D;
output A;
-------
Can I use some kind of //autoarg or //autosense kind of AUTOS to
automatically expand the "verilog statement" (A=B+c|D;) into the the
input/output defines ?
I got some help from
http://www.veripool.com/verilog-mode_veritedium.html
regarding autos but it didn't answer my question.
Any help will greatly be appreciated
Thanks,
Srinivas Lingam
sriniva...@intel.com
Utku Ozcan
When the automation of this kind splash to all parts of
HDL programming, in a few years we won't need to write HDLs!!
An electrode on the brain will "sense" the algorithm and will
translate the "idea" on the fly to HDL code and we all engineers
will be stuck-at-1!! No Emacs, no HDL, no back-end tools etc!
Utku
Robert Szczygiel
> Can i some how automatically generate:
>
> -------
> input B;
> input C;
> input D;
> output A;
> -------
Hi, I would suggest writing a short perl script...
Robert
Illan
Yes Unix script can make your life much more easier as well as it can
make your verification extremly efficient.
a small example is instantiation of module , let say you have a module
name test which is like :
module test (
sel ,
out1 ,
out2 ,
clk ,
rstn
);
input [2:0] sel ;
output [2:0] out1 ;
output [2:0] out2 ;
input clk ;
input rstn ;
...
and you want to instantiate it than you can use for example the
folling unix script :
awk '/module/,/;/ {print}' testx.v | egrep -v "module|;" | sed
's/,.*$//' | awk '{printf".%s (%s),\n",$1,$1}'
and Walla you get a result of :
.sel (sel),
.out1 (out1),
.out2 (out2),
.clk (clk),
.rstn (rstn),
as for input/output in some cases it might be more harder as you need
to tell the width and this is not always easy to tell
but for example is a file test.v have a line saying :
assign a = b | c & d ;
runing the following
awk 'BEGIN{var="output"}{if (NF>0) {for(i=1;i<=NF;i=i+1){if($i ==
"="){var="input"} else {printf"%s\t%s\n",var,$i}}} }' < test.v | egrep
-v "assign|;|&|\|" | sed 's/.*$/&;/'
will give a result of :
output a;
input b;
input c;
input d;
one thing which is importent is that to be consistance in the way you
write as otherwise you will need to adjust the script.
even the above will need few modification as you use different logic
command as for example is you want to use && than you need to replace
the
egrep -v "assign|;|&|\|"
with
egrep -v "assign|;|&|\|&&|"
and I'm sure thre are also quicker and simpler way only that's the
first that jump my mind now.
have a nice day
Illan
Robert Szczygiel <Robert.S...@cern.ch> wrote in message news:<3C15BFD6...@cern.ch>...
jok
Hi. You need to define your inputs and outputs of your module as a minimum.
This goes back to Norton and Thevenin equivalents.
Once you know this, you can leverage off of the autoarg for I/O.
The sensitivity list is related to autosense, but this is to create the
always @(blah blah...), not the input to a module.
Not clear to me why you are declaring inputs and outputs for this statement,
unless the adder is a module in contrast to being a process within a
module.
Cheers,
Jim
"Srinivas Lingam - DPG/FDC" <sli...@pcocd2.intel.com> wrote in message
news:Pine.LNX.4.33.0112102135470.22938-100000@filc6478...
>
> Hi,
>
> If i have a verilog statement
>
> assign A = B + C | D;
>
> Can i some how automatically generate:
>
> -------
> input B;
> input C;
> input D;
> output A;
> -------
>
> Can I use some kind of file://autoarg or file://autosense kind of AUTOS to