Passing verilog Input File as a command line define
SB
I have a Verilog TB that reads from an input file in the following
way:
$readmemb("<configuration_input_file.txt>", config_array);
This Verilog TB is used my multiple runs at the same time
and the configuration_input_file will not be the same for all
the runs.
Is it possible that I can generalize the above command,
so that I can pass the name of the input file to the TB,
using a define such as
$readmemb("INPUT_FILE", config_array);
Then on the command line I will specify something like:
verilog_simulator <tb_file> <verilog_files> +INPUT_FILE=config004.txt
This is not working for me. What am I doing wrong or is there
another way to acheive this?
Cheers
SB
Kevin Neilson
If INPUT_FILE is a parameter, I don't think you should be putting it in
quotes. If it is in quotes it will get treated as an immediate value
and not as a variable. I think you would call the simulator with
> verilog_sim <tb_file> <verilog_files> +INPUT_FILE="config004.txt"
and the $readmemb command would read:
> $readmemb(INPUT_FILE, config_array);
Because strings are treated as any other register, you should be able to
concatenate them like regular registers, like so:
> verilog_sim <tb_file> <verilog_files> +INPUT_FILE="config"
+INPUT_SUFFIX=".txt"
> $readmemb({INPUT_FILE,"00",4,INPUT_SUFFIX}, config_array);
That should work, but alternatively you could use a compiler directive.
In Modelsim, for example, when you compile, you could use the command:
vlog <verilog_file> +define+INPUT_FILE=config004.txt
and then the $readmemb command would read:
> $readmemb("`INPUT_FILE", config_array);
-Kevin
sh...@cadence.com
>
> Is it possible that I can generalize the above command,
> so that I can pass the name of the input file to the TB,
There are several ways to do this. The first would be to use a macro
invocation for the filename. Most tools will allow you to provide a
value for a macro on the compile line. The disadvantage of this is
that you will need to recompile your design every time you want to
change the filename (assuming you are using a tool that has a compile
step separate from the simulation step).
As an alternative, some tools might allow you to override the value of
a Verilog parameter from the command line. This could be used to set
a parameter to the filename.
The best alternative would probably be to use the Verilog-2001 system
function $value$plusarg. This would look something like
reg [80*8:1] filename;
...
initial begin
if (!$value$plusargs("INPUT_FILE=%s", filename))
$display("no input file specified");
$readmemb(filename, config_array);
end
This will look for a simulator command line argument that starts with
+INPUT_FILE= and then read the following text into filename assuming a
string format. The big advantage is that you don't need to recompile
the design to change the filename. Minor disadvantages include that
your tool must support this Verilog-2001 feature, and that you have to
decide ahead of time how large of a string to allocate space for in
your variable.
Kevin Neilson
>
> > $readmemb({INPUT_FILE,"00",4,INPUT_SUFFIX}, config_array);
>
By the way, I made a mistake above by not treating the number 4 as a
string. What I meant was
> $readmemb({INPUT_FILE,"00",(8'd4+8'h30),INPUT_SUFFIX}, config_array);
Adding 8'h30 to a decimal digit converts it to the proper ASCII code.
-Kevin
aka
"Kevin Neilson" <kevin_...@removethiscomcast.net> wrote in message
news:fk6kp8$d0...@cnn.xsj.xilinx.com...
> In Modelsim, for example, when you compile, you could use the command:
>
> vlog <verilog_file> +define+INPUT_FILE=config004.txt
>
> and then the $readmemb command would read:
>
> > $readmemb("`INPUT_FILE", config_array);
$readmemb( `INPUT_FILE, config_array);
And depending on the simulator and O/S (UNIX/Linux vs Windows),
the command-line might look something like this:
ncverilog +define+INPUT_FILE=\"config004.txt\"
(The \" are necessary...)