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LFSR 32-bit parity generator
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Daku
Mar 12, 2011, 11:21:28 AM3/12/11
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Could some Verilog guru please provide some pointers ? I am trying to
create a LFSR 32 bit
parity generator. I am not sure where exactly
to put the XORs, and the total number of these.
Any example code, etc., or pointers to such
would be of immense help. Thanks in advance.
create a LFSR 32 bit
parity generator. I am not sure where exactly
to put the XORs, and the total number of these.
Any example code, etc., or pointers to such
would be of immense help. Thanks in advance.
Muzaffer Kal
Mar 12, 2011, 2:35:44 PM3/12/11
to
On Sat, 12 Mar 2011 08:21:28 -0800 (PST), Daku <daku...@gmail.com>
wrote:
wrote:
here it is:
http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
--
Muzaffer Kal
DSPIA INC.
ASIC/FPGA Design Services
gabor
Mar 15, 2011, 5:27:33 PM3/15/11
to
That's a great reference. You should note
that the standard for naming the register
bits is [N:1] rather than the more typical
[N-1:0] when you reference the bit numbers
in the table. So for example the 32-bit
maximal LFSR described as 1,2,22,32 includes
the LSB and MSB of the shift register in the
XOR inputs.
-- Gabor
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