What is the difference between St0 and 0? (Modelsim)

[Pouya D]

Likewise for St1 and 1. I've searched the documentation for Modelsim
inside out and can't find any good reason why it writes the vale "0"
for some nets in my waveform and "St0" for others. I assume that St0
means strong0 and St1 means strong1. The manual says that 0 and 1
correspond to strong0 and strong1, so why doesn't it just use 0 and 1?

I know I can ask the wave to be viewed in binary radix, which removes
the St prefix on the values, but this is annoying to do...

Some of my nets are vectors, whose value appears like: "St0 St0 St0
St0", and when I ask for a binary radix instead of symbolic radix I
get "0 0 0 0". The spaces in the representation throw me off and are
quite annoying.

Does anyone know what causes this? I'm using Verilog for FPGA RTL
design so I really don't care about drive strengths.

Thank you,
Pouya

[Pouya D]

Quick edit: Values "St0 St0 St0 St0..." are arrays not vectors so the
spaces make sense.
Pouya

[Jonathan Bromley]

On Sat, 6 Mar 2010 13:59:35 -0800 (PST), Pouya D <alb...@gmail.com>
wrote:

>Likewise for St1 and 1. I've searched the documentation for Modelsim
>inside out and can't find any good reason why it writes the vale "0"
>for some nets in my waveform and "St0" for others. I assume that St0
>means strong0 and St1 means strong1. The manual says that 0 and 1
>correspond to strong0 and strong1, so why doesn't it just use 0 and 1?

I think you'll find that ModelSim always displays the strength
value for nets - it gives the same as you would get from the
%v format specifier in $display. On the other hand, if you
display the value of a variable it of course has no strength
and you get plain undecorated 0/1/x/z.

As you correctly say, switch the radix if you don't like it.
Save a wave.do file after changing the radix, then you can
easily reload it any time you like.
--
Jonathan Bromley

[gabor]

On Mar 6, 5:53 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sat, 6 Mar 2010 13:59:35 -0800 (PST), Pouya D <alba...@gmail.com>

I generally change the default radix in Modelsim.ini to hex.
Then change the signals you want to see some other way. For
Verilog I see no reason to use the "symbolic" radix, which
just clutters up the screen. Maybe if there were real enumerated
types, like in VHDL, I would use it for those variables.

Regards,
Gabor

[adee...@gmail.com]

how should we give values for inout ports in modelsim

[Robert Miles]

The way I did it in other Verilog programs was to always give an input
value;
0/1/x when the inout port was used as an input, z when it was used as an
output.

I've never used ModelSim, so I can't check if this works in ModelSim.

[somes...@gmail.com]

For input and output ports, First copy the content from object window to wave window.
Then right click on the input and select "Force". In the newly popped window select value as "0" or "1". So that the value is initiated. Then while running, the value is forced and you can see the expected change at the output.