concatenation with a for loop
fpgaasicdesigner
How can I write more with more elegance this:
header={register[0],register[1],register[2]}.
Meaning having a for loop to concatenate these bus ?
Thanks
Cary R.
localparam max = 2;
for (idx=0; idx<=max; idx=idx+1)
header[(max-idx)*<width> +: <width>] = register[idx];
<width> is the width of the register words.
Cary
John_H
wrote:
A generate statement is the way to go for a wide bus. There really is
no clean way to reverse the order of a bus so the "generate for" will
take care of it in a somewhat better fashion. But if you have few
elements, just write it out. Even 16 elements can come out clean with
4 rows of 4 elements each all lined up under each other in a visible
grid.
header <= { register[ 0], register[ 1], register[ 2], register[ 3]
, register[ 4], register[ 5], register[ 6], register[ 7]
, register[ 8], register[ 9], register[10], register[11]
, register[12], register[13], register[14], register
[15] };
It's possible to use bit manipulation or perhaps the width syntax
header[n] <= register[ n-1 :+ 1 ];
to use a normal for loop but things really start to look unclear to
the reader.
John_H
Oops...
Make that register[ 15-n :+ 1 ]
John_H
Ans as Cary pointed out, it's +: not :+
I guess the day's gotten the better of me.
fpgaasicdesigner
thanks guys, that works with
header[idx*WIDTH +: WIDTH] <= register[idx]
Cary R.
> thanks guys, that works with
> header[idx*WIDTH +: WIDTH] <= register[idx]
except this gives you:
header = {register[2], register[1], register[0]};
not
header = {register[0], register[1], register[2]};
like you originally asked for. I'm just noting a discrepancy. What
matters is that it is working like you expect.
Cary
fpgaasicdesigner
correct... you know it's never in the sense/direction you wanted 2,1,0
or 0,1,2 whatever or 1'b1 instead of been 1'b0 whatever lol
binary digital is funny if you don't have a 1 you will have a 0, so it
never can been wrong ?
thanks guys for the fast answers
and I didn't know this syntax +:, very interesting syntax...
fpgaasicdesigner
and I didn't used an array structure cause it goes to an output I/O of
a module. That cannot be done in Verilog, that's annoying sometimes
and there's no difference in the synthesized result for an array or a
vector, cause an vector is a just a one dimension array... I was able
to do it in VHDL. Perhaps System Verilog is able to do that ?
Jonathan Bromley
>and I didn't used an array structure cause it goes to an output I/O of
>a module. That cannot be done in Verilog, that's annoying sometimes
>and there's no difference in the synthesized result for an array or a
>vector, cause an vector is a just a one dimension array... I was able
>to do it in VHDL.
Yes, VHDL has always been a much more expressive language
for synthesisable designs. Only now is SystemVerilog
beginning to catch up.
> Perhaps System Verilog is able to do that ?
Yes, it is. Ports can be of any array type, and all the
new user-definable data types (struct, union, enum) can
also go on ports. At last!
And the great majority of mainstream tools now fully
support that part of SystemVerilog for both simulation
and synthesis.
--
Jonathan Bromley