Verilog source code for Simple Bus Arbiter

[Sedat Sengul]

Hi;
I am very new to Verilog world. But i am eager to learn.
Can anybody refer me a verilog code for bus arbiter that i can use to
control CPU access and Ethernet controller access(which is using DMA) to
32-bit adress 32-bit data bus.
Thanks
Sedat

[VhdlCohen]

Your question is not really a verilog question because the first question to
address is:
What are your requirements? There are several styles of bus arbiters, fixed
priority, rotating priority, programmable priority, enables, etc...
Below is an example of a fixed priority, with MSB winning over lower order
bits.

module leadone (
// Outputs
ack,
// Inputs
req
);
parameter WIDTH = 8;
input [WIDTH-1:0] req; // bus request
output [WIDTH-1:0] ack; // bus acknowledge
reg [WIDTH-1:0] ack;
integer i; // loop index

always @ (req ) begin : priority
ack = {WIDTH{1'b0}};
for (i=WIDTH-1; i>0; i=i-1) begin
if (req[i]) begin
ack[i] = 1'b1;
disable priority;
end
end
end
endmodule

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

[Edwin Grigorian]

There's a minor bug with this code in that the LSB will never be granted
access.
To fix this, change i>0 in the conditional test of the FOR loop to i>=0.
-EG

"VhdlCohen" <vhdl...@aol.com> wrote in message
news:20020331210031...@mb-cg.aol.com...

[yudhvirs...@gmail.com]

sir i want to design a display using encoder in which i have to design a quiz buzzer ...in this once a person gets priority if two persons simulataneously hit the button..he will not get again and thus the other person gets priority...sir can you plzz tell me how to do it..i tried it using a flag in which i toggle it after each iteration...

[rickman]

yudhvirs...@gmail.com wrote on 6/20/2017 9:49 AM:
> On Thursday, April 4, 2002 at 12:53:23 AM UTC+5:30, Edwin Grigorian wrote:
>
> sir i want to design a display using encoder in which i have to design a quiz buzzer ...in this once a person gets priority if two persons simulataneously hit the button..he will not get again and thus the other person gets priority...sir can you plzz tell me how to do it..i tried it using a flag in which i toggle it after each iteration...

You are replying to a 15 year old post.

What you describe is exactly how I would do it. The state of the flag
indicates which user gets priority. The point that is not entirely clear to
me is how the flag is changed. Is it only changed when the two buttons are
pressed simultaneously? Or every time the button is pressed?

--

Rick C

[jeffrey...@gmail.com]

If you are a new guy to learning Verilog, you must learn easy code first.

[krishnan...@gmail.com]

`timescale 1ns / 1ns

////////////////////////////////////////////////////////////////////////////////
// Arbiter - Unit 1 has priority but does not pre-empt a unit 2 grant. //
////////////////////////////////////////////////////////////////////////////////

module arbiter
(
input wire REQ1, REQ2,
output reg gnt1, gnt2
);

initial begin
gnt1 = 0;
gnt2 = 0;
forever begin
@(REQ1 or REQ2); // requests change
gnt1 <= REQ1 && !REQ2 // no contention
|| REQ1 && REQ2 && !gnt2; // 1 has priority
gnt2 <= REQ2 && !REQ1 // no contention
|| REQ2 && REQ1 && gnt2; // no pre-emption
end
end

endmodule


////////////////////////////////////////////////////////////////////////////////
// Requester - At random intervals needs one or the other or both resources. //
////////////////////////////////////////////////////////////////////////////////

module requester
#(
parameter integer SEED=1
)
(
input wire GNTA, GNTB,
output reg REQA, REQB
);

// TO DO - Define a watchdog task that after a reasonable amount of time
// (the solution uses 17 ns) drops both request signals and disables
// the request loop. The request loop will immediately restart.



initial begin : REQUEST
integer seed;
seed = SEED;
REQA = 0;
REQB = 0;
forever begin : LOOP
#($dist_uniform(seed,1,3));
REQA = $random;
REQB = $random;
// TO DO - Change each wait statement to a parallel block that:
// - Enables the watchdog task
// - Waits for the grant and when it comes disables the task
if (REQA) wait (GNTA);
if (REQB) wait (GNTB);
end
end

endmodule


////////////////////////////////////////////////////////////////////////////////
// Test - Instantiates two requesting units and two responding arbiters //
////////////////////////////////////////////////////////////////////////////////

module test;

wire req1a, req1b, gnt1a, gnt1b;
wire req2a, req2b, gnt2a, gnt2b;

requester #(42) r1 ( gnt1a, gnt1b, req1a, req1b ); // requests A first
requester #(86) r2 ( gnt2b, gnt2a, req2b, req2a ); // requests B first
arbiter aa ( req1a, req2a, gnt1a, gnt2a ); // gives requester 1 priority
arbiter ab ( req2b, req1b, gnt2b, gnt1b ); // gives requester 2 priority

initial
begin : MONITOR
integer mcd;
$timeformat (-9,0,"",4);
mcd = $fopen("outfile.txt");
$fdisplay (mcd,"time r1 r2 g1 g2");
$fmonitor (mcd,"%t %b%b %b%b %b%b %b%b",
$time,req1a,req1b,req2a,req2b,gnt1a,gnt1b,gnt2a,gnt2b);
#99 $finish;
end

endmodule







//// this is my Verilog code....I want solution for some problem which is mention in command on the code..guys please help me

[ukkalkarv...@gmail.com]

3 bus arbiter verilog code